The present invention ultra-low loss high energy density dielectric layers having femtosecond (10.sup.15 sec) polarization response times within a chip stack assembly to extend impedance-matched electrical lengths and mitigate ringing within the chip stack to bring the operational clock speed of the stacked system closer to the intrinsic clock speed(s) of the semiconductor die bonded within chip stack.

A radio-frequency (RF) device includes a semiconductor substrate, a first field-effect transistor (FET) disposed on the substrate, the first FET having a first plurality of drain fingers, and a second FET connected in series with the first FET along a first dimension, the second FET having a second plurality of drain fingers that extent in a second dimension that is orthogonal with respect to the first dimension.

A microwave module includes an RF device and a multilayer resin substrate. The device includes a metal cover covering at least an internal circuit. The substrate includes a first end face on a side of the device, a second end face on a side opposite to the first end face, a signal through-holes surrounding the circuit and connected to the circuit, ground through-holes surrounding the signal through-holes and connected to the cover, a first surface ground provided on the first end face and connected to the cover, an inner layer surface ground connected to ground through-holes, and an RF transmission line surrounded by the ground through-holes, the first surface ground, and the inner layer surface ground, and connected to the signal through-hole.

A number of diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, a diode limiter includes a first diode having a first doped region formed to a first depth into an intrinsic layer of a semiconductor structure, a second diode having a second doped region formed to a second depth into the intrinsic layer of the semiconductor structure, and at least one passive component. The first diode includes a first effective intrinsic region of a first thickness, the second diode includes a second effective intrinsic region of a second thickness. The first thickness is greater than the second thickness. The passive component is over the intrinsic layer and electrically coupled as part of the diode limiter.

A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.

A power module includes: an insulation layer, a plurality of conductive layers, a decoupling capacitor, and a plurality of first components, where the insulation layer includes a plurality of sub-insulation layers stacked in a thickness direction of the power module, and the sub-insulation layer is disposed between every two adjacent conductive layers. The first component is located at a sub-insulation layer in a first region and is electrically connected to a conductive layer adjacent to the sub-insulation layer at which the first component is disposed, and at least some of the first components are stacked in the thickness direction of the power module. The insulation layer located in the first region has an auxiliary accommodation cavity, the decoupling capacitor is located in the auxiliary accommodation cavity, the pins of the decoupling capacitor is electrically connected to the plurality of conductive layers.

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a 3D metal insulator metal (MIM) capacitor structure with an increased capacitance per unit area in a semiconductor structure. The MIM structure includes a substrate, an oxide layer formed over the substrate, and a first metal layer formed over the oxide layer. The first metal layer includes a plurality of mandrels formed on a surface of the first metal layer. The MIM structure also includes a dielectric layer formed over the first metal layer and the plurality of mandrels, a second metal layer formed over on the dielectric layer, and one or more interconnect structures electrically connected to the first and second metal layers.

A housing for a high-frequency chip in a radar device for level measurement is provided, including a high-frequency chip having a high-frequency terminal and a supply terminal; horizontal metal layers; vertical metal connecting lines; and an external supply terminal configured to connect the chip to a circuit board of the device, the chip being attached to one of the horizontal metal layers in an electrically conductive manner, and being embedded in a polymer compound, which is located between the horizontal metal layers, the supply terminal being connected to the external supply terminal via at least one of the horizontal metal layers and via at least one of the vertical metal connecting lines, and the high-frequency terminal being connected to an antenna configured to decouple and receive radar waves, via at least one of the horizontal metal layers and/or via at least one of the vertical metal connections.

In a switching module structure that includes a low-impedance path to ground, such as a parasitic capacitance of an insulating substrate, a further insulating substrate presenting a parasitic capacitance placed in series with the low impedance current path and a connection of a conductive layer to input voltage rails using a single decoupling capacitor or, preferably, a midpoint of the voltage rails formed by a series connection of decoupling capacitors maintains a large portion of common mode (CM) currents which are due to high dV/dt slew rates of SiC and GaN transistors within the switching module.

In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component.