The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a 3D metal insulator metal (MIM) capacitor structure with an increased capacitance per unit area in a semiconductor structure. The MIM structure includes a substrate, an oxide layer formed over the substrate, and a first metal layer formed over the oxide layer. The first metal layer includes a plurality of mandrels formed on a surface of the first metal layer. The MIM structure also includes a dielectric layer formed over the first metal layer and the plurality of mandrels, a second metal layer formed over on the dielectric layer, and one or more interconnect structures electrically connected to the first and second metal layers.

An electronic package includes a package substrate of a rectangular shape, and a chip package including a first interface circuit die and a second interface circuit die. The first interface circuit die and second interface circuit die are mounted on a redistribution layer structure and encapsulated within a molding compound. The chip package is mounted on a top surface of the package substrate and rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through a rotation offset angle. A metal ring is mounted on the top surface of the package substrate.

A multi-chip module (MCM) package includes an organic laminate substrate; first and second semiconductor device chips that are mounted to a top side of the substrate and that define a chip gap region between opposing edges of the chips; and a stiffener that is embedded in the bottom side of the substrate. The stiffener extends across a stiffening region, which underlies the chip gap region, and does not protrude beyond a bottom side metallization of the substrate.

A microwave device includes: a first multilayer resin substrate including a ground via hole; a semiconductor substrate provided at the first multilayer resin substrate and including a high frequency circuit; and a conductive heat spreader provided at an opposite face of the semiconductor substrate from a face of the semiconductor substrate facing the first multilayer resin substrate. The microwave device includes: a resin provided over the first multilayer resin substrate and covering the semiconductor substrate and the heat spreader such that an opposite face of the heat spreader from a face of the heat spreader facing the semiconductor substrate is exposed as an exposed face; and a conductive film covering the resin and the heat spreader and touching the exposed face. The semiconductor substrate includes a ground through hole extending through the semiconductor substrate. The conductive film is electrically connected to the ground via hole via the heat spreader and the ground through hole.

A multi-chip module (MCM) package includes an organic laminate substrate; first and second semiconductor device chips that are mounted to a top side of the substrate and that define a chip gap region between opposing edges of the chips; and a stiffener that is embedded in the bottom side of the substrate. The stiffener extends across a stiffening region, which underlies the chip gap region, and does not protrude beyond a bottom side metallization of the substrate.

The present disclosure provides a power module including a transformer, a first switching unit and a second switching unit; the transformer includes a magnetic core and a flatwise-wound winding wound around a winding pillar of the magnetic core; the flatwise-wound winding includes a first winding, a first end of the first winding and the first switching unit are electrically connected and are located on the first side face of the winding pillar, projections of the first switching unit, the first end of the first winding, and the winding pillar on the first side face overlap each other; a second end of the first winding and the second switching unit are electrically connected and are located on the second side face of the winding pillar, projections of the second switching unit, the second end of the first winding, and the winding pillar on the second side face overlap each other.

A number of monolithic diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, two PIN diodes in a diode limiter semiconductor structure have different intrinsic region thicknesses. The first PIN diode has a thinner intrinsic region, and the second PIN diode has a thicker intrinsic region. This configuration allows for both the thin intrinsic region PIN diode and the thick intrinsic region PIN diode to be individually optimized. The thin intrinsic region PIN diode can be optimized for low level turn on and flat leakage, and the thick intrinsic region PIN diode can be optimized for low capacitance, good isolation, and high incident power levels. This configuration is not limited to two stage solutions, as additional stages can be used for higher incident power handling.

In described examples of a circuit module, a multilayer substrate has a conductive pad formed on a surface of the multilayer substrate. An integrated circuit (IC) die is bonded to the surface of the substrate in dead bug manner, such that a set of bond pads formed on a surface of the IC die are exposed. A planar interconnect line formed by printed ink couples the set of bond pads to the conductive pad.

Systems and methods for placing capacitors between IC bumps and BGA balls are described. In one embodiment, the method may include placing a ball grid array (BGA) package or integrated circuit (IC) package on a printed circuit board (PCB) of an electronic device, and placing a capacitor between a first BGA ball and a second BGA ball of the BGA package and/or placing a capacitor between a first IC bump and a second IC bump of the IC package to maintain impedance of a power delivery network (PDN) of the BGA package or IC package below a target impedance.

A radio frequency amplifier includes a transistor, an input impedance matching circuit (e.g., a single-section T-match circuit or a multiple-section bandpass circuit), and a fractional harmonic resonator circuit. The input impedance matching circuit is coupled between an amplification path input and a transistor input terminal. An input of the fractional harmonic resonator circuit is coupled to the amplification path input, and an output of fractional harmonic resonator circuit is coupled to the transistor input terminal. The fractional harmonic resonator circuit is configured to resonate at a resonant frequency that is between a fundamental frequency of operation of the RF amplifier and a second harmonic of the fundamental frequency. According to a further embodiment, the fractional harmonic resonator circuit resonates at a fraction, x, of the fundamental frequency, wherein the fraction is between about 1.25 and about 1.9 (e.g., x≈1.5).