A semiconductor package includes a redistribution substrate including a first surface and a second surface that are opposite to each other, an antenna substrate on the first surface and including a first insulating portion and antenna patterns on a top surface of the first insulating portion, and a first semiconductor chip on the second surface. The redistribution substrate includes a second insulating portion, and a redistribution pattern in the second insulating portion. The redistribution pattern includes an interconnection portion extending parallel to a top surface of the second insulating portion, and a via portion protruding from the interconnection portion toward the first surface. A width of the via portion decreases as a height in a direction from the second surface toward the first surface increases. The active surface of the first semiconductor chip is adjacent to the second surface.

A wafer-level ASIC 3D integrated substrate, a packaging device and a preparation method are disclosed. The substrate includes a first wiring layer conductive pillars, a molding layer, a second wiring layer, a bridge IC structure and solder balls. The first wiring layer includes a first dielectric layer and a first metal wire layer. The second wiring layer includes a second dielectric layer and a second metal wire layer. The conductive pillars are disposed between the first wiring layer and the second wiring layer, two ends of each of the conductive pillars are electrically connected to the first metal wire layer and the second metal wire layer, respectively. The bridge IC structure is electrically connected to at least one conductive pillar. The molding layer molds the conductive pillars and the bridge IC structure. The solder balls are disposed on a side of the second wiring layer and electrically connected to the second metal wire layer.

Waveguide interconnects for semiconductor packages are disclosed. An example semiconductor package includes a first semiconductor die, a second semiconductor die, and a substrate positioned between the first and second dies. The substrate includes a waveguide interconnect to provide a communication channel to carry an electromagnetic signal. The waveguide interconnect is defined by a plurality of through substrate vias (TSVs). The TSVs in a pattern around the at least the portion of the substrate to define a boundary of the communication channel.

A wireless transmission module, chips, a passive component, and a coil are integrated into an integral structure, so that an integration level of the wireless transmission module is improved. In addition, the integral structure can effectively implement independence of the module, and the independent module can be flexibly arranged inside structural design of an electronic device, and does not need to be disposed on a mainboard of the electronic device. Only an input terminal of the wireless transmission module needs to be retained on the mainboard of the electronic device. In addition, the integral structure can further effectively increase a capability of a product for working continuously and normally in an extremely harsh scenario, and improve product reliability. In addition, in the structure of the wireless transmission module, the chips and the coil are integrated, and signal transmission paths between the chips and the coil are relatively short.

An integrated radar circuit comprising: a first substrate, of a first semiconductor material, said first substrate comprising an integrated transmit and receive radar circuit; a second substrate, of a second semiconductor material, said second substrate comprising at least on through-substrate cavity having cavity walls; at least one discrete transistor chip, of a third semiconductor material, said at least one discrete transistor chip having chip walls and being held in said at least one through-substrate cavity by a metal filling extending from at least one cavity wall to at least one chip wall; a conductor on said second substrate, electrically connecting a portion of said integrated transmit and receive radar circuit to a discrete transistor on said at least one discrete transistor chip.

Disclosed is a packaging structure for circuit units, comprising: a circuit baseplate, wherein the circuit baseplate is provided thereon with a circuit unit, the circuit unit including a silicon dioxide layer and an electronic device arranged on the silicon dioxide layer; an insulator, wherein the insulator surrounds the circuit unit; and an electromagnetic shielding layer, wherein the electromagnetic shielding layer covers the circuit unit and the insulator.

Embodiments described herein may be related to apparatuses, processes, and techniques related to contactless transmission within a package that combines radiating elements with vertical transitions in the package, in particular to a waveguide within a core of the package that is surrounded by a metal ring. A radiating element on one side of the substrate core and above the waveguide surrounded by the metal ring communicates with another radiating element on the other side of the substrate core and below the waveguide surrounded by the metal ring. Other embodiments may be described and/or claimed.

A wafer stack structure includes an interlayer, a first wafer, and a second wafer. The interlayer has a first surface and a second surface opposite to the first surface. The intermediate layer includes a dielectric material layer and a redistribution layer embedded in the dielectric material layer. The first wafer is disposed on the first surface of the interlayer. The second wafer is disposed on the second surface of the interlayer. The second wafer is electrically connected to the first wafer through the redistribution layer of the interlayer.

Embodiments disclosed herein comprise package substrates and methods of forming such package substrates. In an embodiment, a package substrate comprises a core, where the core comprises glass. In an embodiment, an opening if formed through the core. In an embodiment, a magnetic region is disposed in the opening.

An integrated circuit (IC) includes a semiconductor substrate having a first surface and a second surface opposite the first surface. A through wafer trench (TWT) extends from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate. Dielectric material is in the TWT. An interconnect region has layers of dielectric on the first surface of the substrate. The interconnect region has a conductive transmit patch. An antenna is formed, at least in part, by the dielectric material in the TWT and the transmit patch in the interconnect region. The antenna is configured to transmit or receive electromagnetic radiation between the transmit patch and the second surface of the semiconductor substrate through the dielectric material within the trench.