Patent classifications
H01L2224/02311
SEMICONDUCTOR PACKAGE AND METHOD MANUFACTURING THE SAME
A semiconductor package including an insulating encapsulation, an integrated circuit component, and conductive elements is provided. The integrated circuit component is encapsulated in the insulating encapsulation, wherein the integrated circuit component has at least one through silicon via protruding from the integrated circuit component. The conductive elements are located on the insulating encapsulation, wherein one of the conductive elements is connected to the at least one through silicon via, and the integrated circuit component is electrically connected to the one of the conductive elements through the at least one through silicon via.
LTHC as charging barrier in InFO package formation
A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.
PACKAGING STRUCTURE AND FABRICATION METHOD THEREOF
Packaging structure and fabrication method are provided. The method includes: providing semiconductor chips; providing soldering pads on the semiconductor chips, a metal bump on each soldering pad, and a first plastic encapsulation layer on functional surfaces of the semiconductor chips; providing a carrier plate; adhering the first plastic encapsulation layer on the functional surfaces of the semiconductor chips to the carrier plate; forming a first shielding layer covering non-functional surfaces and sidewalls of the semiconductor chips; forming a second shielding layer on the first shielding layer; forming a second plastic encapsulation layer on the second shielding layer and on the carrier plate between semiconductor chips; peeling off the carrier plate to form a pre-packaging plate; removing a portion of the first plastic encapsulation layer to expose the metal bumps; forming an external contact structure on the backside of the pre-packaging plate and connected to each metal bump.
Alternative integration for redistribution layer process
In one example, a method for redistribution layer (RDL) process is described. A substrate is provided. A dielectric layer is deposited on top of the substrate. The dielectric layer is patterned. A barrier and copper seed layer are deposited on top of the dielectric layer. A photoresist layer is applied on top of the barrier and copper seed layer. The photoresist layer is patterned to correspond with the dielectric layer pattern. Copper is electrodepositing in the patterned regions exposed by the photoresist layer. The photoresist layer is removed. The copper and seed barrier are etched.
DIFFERENTIAL CONTRAST PLATING FOR ADVANCED PACKAGING APPLICATIONS
A method of electroplating a metal into features, having substantially different depths, of a partially fabricated electronic device on a substrate is provided. The method includes adsorbing accelerator into the bottom of recessed features; partially filling the features by a bottom up fill mechanism in an electroplating solution; diffusing leveler into shallow features to decrease the plating rate in shallow features as compared to deep features; and electroplating more metal into the features such that the height of metal in deep features is similar to the height of metal in shallow features.
DIFFERENTIAL CONTRAST PLATING FOR ADVANCED PACKAGING APPLICATIONS
A method of electroplating a metal into features, having substantially different depths, of a partially fabricated electronic device on a substrate is provided. The method includes adsorbing accelerator into the bottom of recessed features; partially filling the features by a bottom up fill mechanism in an electroplating solution; diffusing leveler into shallow features to decrease the plating rate in shallow features as compared to deep features; and electroplating more metal into the features such that the height of metal in deep features is similar to the height of metal in shallow features.
Dummy structure of stacked and bonded semiconductor device
A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.
SEMICONDUCTOR STRUCTURE INCLUDING BUFFER LAYER
A semiconductor structure includes a first contact pad over an interconnect structure. The semiconductor structure further includes a second contact pad over the interconnect structure, wherein the second contact pad is electrically separated from the first contact pad. The semiconductor structure further includes a first buffer layer over the first contact pad, wherein the first buffer layer is partially over the second contact pad, and an edge of the second contact pad farthest from the first contact pad extends beyond the first buffer layer.
FLEXIBLE ELECTRONIC STRUCTURE
There is provided a flexible electronic structure for bonding with an external circuit, comprising a flexible substrate, having a first surface, configured for bonding with the external circuit, and an opposing second surface, configured for engagement with a bonding tool, comprising at least one electronic component; at least one contact member, operatively coupled with said at least one electronic component and provided at said first surface of said flexible substrate, and adapted to operably interface with the external circuit after bonding, and at least one shield member, provided at said first surface so as to shieldingly overlap at least a portion of said at least one electronic component, adapted to withstand a predetermined pressure applied to said first surface and/or said opposing second surface during bonding with the external circuit.
FLEXIBLE ELECTRONIC STRUCTURE
There is provided a flexible electronic structure for bonding with an external circuit. The flexible electronic structure comprising: a flexible body having a first surface, the flexible body comprising at least one electronic component; at least one contact element configured to bond with the external circuit, the at least one contact element operatively coupled with the at least one electronic component and provided at the first surface of the flexible body, and arranged to operably interface with the external circuit after bonding, and at least one support element provided at the first surface of the flexible body, each support element arranged to contact a corresponding surface element disposed on a first surface of an external structure comprising the external circuit.