A semiconductor device includes a first conductive element electrically connected to an interconnect structure, wherein the first conductive element includes a first conductive material. The semiconductor device further includes an RDL over the first conductive element and electrically connected to the first conductive element, wherein the RDL includes a second conductive material different from the first conductive material. The semiconductor device further includes a passivation layer over the RDL, wherein a top portion of a sidewall of the second passivation layer includes a convex curve protruding in a direction parallel to a top surface of the interconnect structure, a width of the top portion at a bottom of the convex curve is less than a width of the top portion at a middle of the convex curve, and the middle of the convex curve is above the bottom of the convex curve.

A chip module is provided. The chip module includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a signal pad region adjacent to the upper surface. A recess extends from the upper surface toward the lower surface along the sidewall of the chip. A redistribution layer is electrically connected to the signal pad region and extends into the recess. A circuit board is located between the upper surface and the lower surface and extends into the recess. A conducting structure is located in the recess and electrically connects the circuit board to the redistribution layer. A method for forming the chip module is also provided.

A method includes forming a first plurality of redistribution lines, forming a first metal post over and electrically connected to the first plurality of redistribution lines, and bonding a first device die to the first plurality of redistribution lines. The first metal post and the first device die are encapsulated in a first encapsulating material. The first encapsulating material is then planarized. The method further includes forming a second metal post over and electrically connected to the first metal post, attaching a second device die to the first encapsulating material through an adhesive film, encapsulating the second metal post and the second device die in a second encapsulating material, planarizing the second encapsulating material, and forming a second plurality of redistributions over and electrically coupling to the second metal post and the second device die.

A method of fabricating a package includes providing a mold substrate supporting dies in cavities of a fan-out substrate, detecting positions of the dies with respect to the fan-out substrate, and forming interconnection lines. At least one of the interconnection lines includes a first portion extending from the fan-out substrate to a target position on the cavity disposed between the fan-out substrate and one of the dies the one of the dies disposed at a detected position different from the target position, and a second portion extending from the one die to the fan-out substrate.

A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a pattern layer disposed on the encapsulant and covering at least portions of the encapsulant adjacent to the inactive surface of the semiconductor chip; vias penetrating through the encapsulant and connecting the pattern layer and the inactive surface of the semiconductor chip to each other; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip.

Mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.

A method includes bonding a first device die and a second device die to a substrate, and filling a gap between the first device die and the second device die with a gap-filling material. A top portion of the gap-filling material covers the first device die and the second device die. Vias are formed to penetrate through the top portion of the gap-filling material. The vias are electrically coupled to the first device die and the second device die. The method further includes forming redistribution lines over the gap-filling material using damascene processes, and forming electrical connectors over and electrically coupling to the redistribution lines.

PoP devices and methods of forming the same are disclosed. A PoP device includes a first package structure and a second package structure. The first package structure includes a first chip, and a plurality of active through integrated fan-out vias and a plurality of dummy through integrated fan-out vias aside the first chip. The second package structure includes a plurality active bumps bonded to the plurality of active through integrated fan-out vias, and a plurality of dummy bumps bonded to the plurality of dummy through integrated fan-out vias. Besides, a total number of the active through integrated fan-out vias and the dummy through integrated fan-out vias at a first side of the first chip is substantially the same as a total number of the active through integrated fan-out vias and the dummy through integrated fan-out vias at a second side of the first chip.

A semiconductor device package and method of manufacturing is provided. An interconnect pre-assembly includes a first frame having a plurality of first signal conduits affixed to a second frame having a plurality of second signal conduits embedded in a second substrate forming an electrical coupling between one or more first signal conduits and one or more of the second signal conduits. One or more conductive balls are connected to the one or more second signal conduits. The interconnect pre-assembly is placed over a semiconductor die, having at least one of the first conductive balls disposed over the semiconductor die. An encapsulant encapsulates the interconnect pre-assembly, the semiconductor die, and the one or more conductive balls, such that a portion of the one or more first conductive balls is exposed at a top surface of the encapsulant.

A fan-out wafer level package includes a semiconductor die with a redistribution layer on a sidewall of the semiconductor die. A redistribution layer positioned over the die includes an extended portion that extends along the sidewall. The semiconductor die is encapsulated in a molding compound layer. The molding compound layer is positioned between the extended portion of the redistribution layer and the sidewall of the semiconductor die. Solder contacts, for electrically connecting the semiconductor device to an electronic circuit board, are positioned on the redistribution layer. The solder contacts and the sidewall of the redistribution layer can provide electrical contact on two different locations. Accordingly, the package can be used to improve interconnectivity by providing vertical and horizontal connections.