The present application discloses a method for fabricating a semiconductor device with graphene layers The method includes providing a substrate; forming a first passivation layer above the substrate; forming a redistribution layer on the first passivation layer; forming a first adjustment layer on the redistribution layer; forming a pad layer on the first adjustment layer; forming a second adjustment layer between the pad layer and the first adjustment layer; forming a second passivation layer on the first passivation layer; wherein the first adjustment layer and the second adjustment layer are formed of graphene.

The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes a substrate, a conductive feature, a redistribution layer, at least one through silicon via and at least one bump. The conductive feature is disposed over a front surface of the substrate, and the redistribution layer is disposed over a back surface opposite to the front surface. The through silicon via penetrates through the substrate and contacts the conductive feature embedded in an insulative layer. The bump contacts the redistribution layer and the through silicon via and serves as an electrical connection therebetween.

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a conductive feature, a redistribution layer, at least one through silicon via and at least one bump. The conductive feature is disposed over a front surface of the substrate, and the redistribution layer is disposed over a back surface opposite to the front surface. The through silicon via penetrates through the substrate and contacts the conductive feature embedded in an insulative layer. The bump contacts the redistribution layer and the through silicon via and serves as an electrical connection therebetween.

The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor component, a re-routing layer, a bonding dielectric and an insulating layer. The re-routing layer is disposed over the semiconductor component and electrically coupled to the semiconductor component. The bonding dielectric is disposed over the semiconductor component to surround a top portion of the re-routing layer. The insulating layer is disposed between the semiconductor component and the bonding dielectric to surround a bottom portion of the re-routing layer.

Wafer level passive array packages, modules, and methods of fabrication are described. In an embodiment, a module includes a circuit board, and a package mounted on the circuit board in which the package includes a plurality of passive components bonded to a bottom side of the die and a plurality of landing pads of the circuit board.

The present application discloses a semiconductor device with graphene layers and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first passivation layer positioned above the substrate, a redistribution layer positioned on the first passivation layer, a first adjustment layer positioned on the redistribution layer, a pad layer positioned on the first adjustment layer, and a second adjustment layer positioned between the pad layer and the first adjustment layer. The first adjustment layer and the second adjustment layer are formed of graphene.

The present application discloses a method for fabricating a semiconductor device. The method includes providing a first chip comprising a first substrate, a first redistribution layer positioned above the first substrate, a first lower bonding pad positioned on the first redistribution layer, and a second lower bonding pad positioned above the first substrate and distant from the first lower bonding pad. The method also includes providing a second chip comprising a dense region and a loose region adjacent to the dense region; a plurality of upper pads positioned on the first lower bonding pad and the second lower bonding pad; and a plurality of second redistribution layers positioned on the plurality of upper pads. The method further performs bonding the second chip onto the first chip in a face-to-face manner, wherein the plurality of upper pads contact the first lower bonding pad and the second lower bonding pad.

A method of forming semiconductor device includes forming interconnect structure over substrate; forming first passivation layer over the interconnect structure, and metal-insulator-metal capacitor in the first passivation layer; forming first redistribution layer including first pads over the first passivation layer, and first vias extending into the first passivation layer; conformally forming second passivation layer over the first redistribution layer and first passivation layer, and patterning the second passivation layer to form via openings exposing the first pads; forming second redistribution layer including second pads over the second passivation layer, and second vias in the first via openings, wherein the first and second redistribution layers include aluminum-copper alloy and copper, respectively; forming dielectric layer over the second redistribution layer, and patterning the dielectric layer to form via openings exposing some second pads; and forming bumps over the dielectric layer and in the via openings to contact exposed second pads.

A chip package with higher bearing capacity in wire bonding is provided. The chip package includes at least one conductive circuit which is a structure with a thickness ranging from 4.5 μm to 20 μm. Thereby a structural strength of the conductive circuit is improved and able to stand a positive pressure generated in wire bonding or formation of a first bonding point. Thus at least one internal circuit of a chip will not be damaged by the positive pressure and allowed to pass through an area under the first bonding point or arrange under the first bonding point. A problem of increased cost at manufacturing end caused by the internal circuit redesign of the chip can be solved effectively. This is beneficial to cost reduction at manufacturing end.

A semiconductor package structure includes a first semiconductor die, a second semiconductor die, a third semiconductor die and an external contact. The second semiconductor die is disposed adjacent to the first semiconductor die. The third semiconductor die electrically connects the first semiconductor die and the second semiconductor die. The external contact is electrically connected to the third semiconductor die. An electrical path between the third semiconductor die and the external contact extends through a space between the first semiconductor die and the second semiconductor die.