A method for fabricating a semiconductor structure includes providing a substrate with a first surface and a second surface, wherein at least one soldering pad is formed on the first surface of the substrate. The method also includes forming at least one via to expose each soldering pad by etching the substrate from the second surface, forming a seed layer to cover the second surface of the substrate and the sidewall and the bottom surfaces of each via, and then forming a redistribution metal layer over a portion of the seed layer formed on the sidewall and the bottom surfaces of each via and the second surface of the substrate surrounding each via. The method further includes alternately performing a pre-wetting process and a chemical etching process to completely remove the portion of the seed layer not covered by the redistribution metal layer.

A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.

A first mask and a second mask are sequentially provided to perform a multi-step exposure and development processes. Through proper overlay design of the first mask and the second mask, conductive wirings having acceptable overlay offset are formed.

An electronic components comprising electronic pillars is provided. An example electronic component, such as an electronic chip, comprising a semiconductor substrate having opposite first and second faces and electrically-conductive pillars intended to be connected to an element external to the electronic component, an insulating layer covering the second surface of the substrate, a first portion of the electrically-conductive pillars projecting from the insulating layer, and a second portion of the electrically-conductive pillars crossing the insulating layer and extending in the semiconductor substrate down to a depth smaller than the thickness of the semiconductor substrate.

A first mask and a second mask are sequentially provided to perform a multi-step exposure and development processes. Through proper overlay design of the first mask and the second mask, conductive wirings having acceptable overlay offset are formed.

A semiconductor device includes a semiconductor element, an electrode located on a first side in a thickness direction of the semiconductor element, a re-wiring located on the first side in the thickness direction with respect to the electrode and electrically connected to the electrode, and a terminal located on the first side in the thickness direction with respect to the re-wiring and electrically connected to the re-wiring. The re-wiring includes a first re-wiring and a second re-wiring. The dimension of the second re-wiring in the thickness direction is greater than the dimension of the first re-wiring in the thickness direction.

A semiconductor device includes a semiconductor element, an electrode on a first side in a thickness direction of the semiconductor element, a re-wiring connected to the electrode, a terminal connected to the re-wiring, and a conductive bonding layer connected to the terminal. The terminal includes a first terminal and a second terminal. The conductive bonding layer includes a first conductive bonding layer connected to the first terminal and a second conductive bonding layer connected to the second terminal. The area of the second terminal is greater than the area of the first terminal. The area of the second conductive bonding layer is greater than the area of the first conductive bonding layer.

The present description provides a method of manufacturing electronic components. The electronic components have wettable flanks. An example method comprises a) providing a substrate having chips formed therein, connection areas being arranged on an upper surface of the substrate, conductive pads being able to cover the connection areas, b) optionally, forming cavities between the chips, c) depositing a layer of insulating material on the substrate and in the cavities, d) making the connection area or conductive pads accessible, e) depositing a layer of conductive material to couple the connection areas of two adjacent chips, f) depositing an additional layer of insulating material, g) thinning the additional layer until the conductive material is accessible, and h) separating the electronic components by dicing through the cavities, provided which the conductive material forms the wettable flanks of the electronic components.