A semiconductor device includes an insulating layer, conductors, a semiconductor element and a sealing resin. The insulating layer has first and second surfaces opposite to each other in the thickness direction. Each conductor has an embedded part whose portion is embedded in the insulating layer and a redistribution part disposed at the second surface and connected to the embedded part. The semiconductor element has electrodes provided near the first surface and connected the embedded parts of the conductors. The semiconductor element is in contact with the first surface. The sealing resin partially covers the semiconductor element and is in contact with the first surface. The redistribution parts include portions outside the semiconductor element as viewed in the thickness direction. The insulating layer has grooves recessed from the second surface in the thickness direction. The redistribution parts are in contact with the grooves.

A semiconductor structure includes a first substrate, a first redistribution line (RDL) pad, and a first bond pad. The first substrate has a first conductive pad. The RDL pad is disposed over the first conductive pad and extending to a top surface of the first substrate. The first bond pad is disposed on a first portion of the first RDL pad, in which the first portion of the first RDL pad overlaps with the top surface of the first substrate.

A semiconductor structure includes a first substrate, a first redistribution line (RDL) pad, and a first bond pad. The first substrate has a first conductive pad. The RDL pad is disposed over the first conductive pad and extending to a top surface of the first substrate. The first bond pad is disposed on a first portion of the first RDL pad, in which the first portion of the first RDL pad overlaps with the top surface of the first substrate.

A semiconductor device includes a first passivation layer over a substrate. The semiconductor device further includes a post passivation interconnect (PPI) line over the first passivation layer, wherein a top-most portion of the PPI line has a first portion having a convex shape and a second portion having a concave shape. The semiconductor device further includes a second passivation layer configured to cause stress to the PPI line. The semiconductor device further includes a polymer material over the second passivation layer.

The present disclosure includes a semiconductor package including a redistribution layer (RDL) having a first surface in contact with input/output (I/O) contacts and a second surface opposite to the first surface. The semiconductor package also includes a staircase interconnect structure formed on the second surface of the RDL and electrically connected with the RDL. The staircase interconnect structure includes staircase layers including a first staircase layer and a second staircase layer stacked on a top surface of the first staircase layer. The second staircase layer covers a portion of the top surface of the first staircase layer such that a remaining portion of the top surface of the first staircase layer is exposed. Integrated circuit (IC) chips are electrically connected to the RDL via the staircase interconnect structure. A first IC chip of the IC chips is electrically connected to the RDL through the remaining portion of the top surface of the first staircase layer.

A method for forming microvias for packaging applications is disclosed. A sacrificial photosensitive material is developed to form microvias with reduced diameter and improved placement accuracy. The microvias are filled with a conductive material and the surrounding dielectric is removed and replaced with an RDL polymer layer.

A method of forming a semiconductor structure includes following steps. The first substrate is etched to form an opening, such that a first conductive pad of the first substrate is exposed through the opening. A first RDL pad is formed over the first conductive pad and extends to a top surface of the first substrate. A first bond pad is formed on a first portion of the first RDL pad, in which the first portion of the first RDL pad overlaps with the top surface of the first substrate.

A method of forming a semiconductor structure includes following steps. The first substrate is etched to form an opening, such that a first conductive pad of the first substrate is exposed through the opening. A first RDL pad is formed over the first conductive pad and extends to a top surface of the first substrate. A first bond pad is formed on a first portion of the first RDL pad, in which the first portion of the first RDL pad overlaps with the top surface of the first substrate.

The present disclosure provides a redistribution layer (RDL) structure, a semiconductor device and manufacturing method thereof. The semiconductor device comprising an RDL structure that may include a substrate, a first conductive layer, a reinforcement layer and, and a second conductive layer. The first conductive layer may be formed on the substrate and has a first bond pad area. The reinforcement layer may be formed on a surface of the first conductive layer facing away from the substrate and located in the first bond pad area. The second conductive layer may be formed on the reinforcement layer and an area of the first conductive layer not covered by the reinforcement layer. The reinforcement layer has a material strength greater than those of the first conductive layer and the second conductive layer. The semiconductor device and the manufacturing method provided by the present disclosure may improve the performance of the semiconductor device.

The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.