A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.

A device and fabrication techniques are described that employ wafer-level packaging techniques for fabricating semiconductor devices that include a pad defined contact. In implementations, the wafer-level package device that employs the techniques of the present disclosure includes a substrate, a passivation layer, a top metal contact pad, a thin film with a via formed therein, a redistribution layer structure configured to contact the top metal contact pad, and a dielectric layer on the thin film and the redistribution layer structure. In implementations, a process for fabricating the wafer-level package device that employs the techniques of the present disclosure includes processing a substrate, forming a passivation layer, depositing a top metal contact pad, forming a thin film with a via formed therein, forming a redistribution layer structure in the via formed in the thin film, and forming a dielectric layer on the thin film and the redistribution layer structure.

In one implementation a wafer processing method includes filling a plurality of through-resist recessed features with a metal, such that a ratio of fill rate of a first feature to a fill rate of a second feature is R1; followed by electrochemically removing metal such that a ratio of metal removal rate from the first feature to the metal removal rate from the second feature is greater than R1, improving the uniformity of the fill. In some embodiments the method includes contacting an anodically biased substrate with an electrolyte such that the electrolyte has a transverse flow component in a direction that is substantially parallel to the working surface of the substrate. The method can be implemented in an apparatus that is configured for generating the transverse flow at the surface of the substrate. In some implementations the method makes use of distinct electrochemical regimes to achieve improvement in uniformity.

In one embodiment of the invention, a method for correcting a pattern placement on a substrate is disclosed. The method begins by detecting three reference points for a substrate. A plurality of sets of three die location points are detected, each set indicative of an orientation of a die structure, the plurality of sets include a first set associated with a first dies and a second set associated with a second die. A local transformation is calculated for the orientation of the first die and the second on the substrate. Three orientation points are selected from the plurality of sets of three die location points wherein the orientation points are not set members of the same die. A first global orientation of the substrate is calculated from the selected three points from the set of points and the first global transformation and the local transformation for the substrate are stored.

A semiconductor device package includes an electronic component, a first set of conductive wires electrically connected to the electronic component, and an insulation layer surrounding the first set of conductive wires. The insulation layer exposes a portion of the first set of the conductive wires. The insulation layer is devoid of a filler.

A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the device die is patterned to extend the opening further into the device die. After patterning, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material.

A microelectronic device is formed by forming a seed layer that contains primarily zinc. A plating mask is formed over the seed layer, and a copper strike layer is formed on the seed layer using a neutral pH copper plating bath. A main copper layer is formed on the copper strike layer by plating copper on the copper strike layer. The plating mask is subsequently removed. The main copper layer, the copper strike layer, and the seed layer are heated to diffuse copper and zinc, and form a brass layer under the main copper layer, consuming the seed layer between the main copper layer and the substrate. Remaining portions of the seed layer are removed by a wet etch process. The main copper layer and the underlying brass layer provide a conductor structure.

Methods and apparatus are disclosed which reduce the stress concentration at the redistribution layers (RDLs) of a package device. A package device may comprise a seed layer above a passivation layer, covering an opening of the passivation layer, and covering and in contact with a contact pad. A RDL is formed above the passivation layer, above and in contact with the seed layer, covering the opening of the passivation layer, and electrically connected to the contact pad through the seed layer. The RDL has an end portion with a surface that is smooth without a right angle. The surface of the end portion of the RDL may have an obtuse angle, or a curved surface.

The present disclosure provides a method for manufacturing a semiconductor structure. The semiconductor structure includes a substrate having a first surface and a second surface opposite to the first surface; a pad disposed over the first surface; a first passivation disposed over the first surface and partially covering the pad; a redistribution layer (RDL) disposed over the first passivation, and including a conductive line extending over the first passivation and a second passivation partially covering the conductive line. The conductive line includes a via portion coupled with the pad and extended within the first passivation towards the pad, and a land portion extended over the first passivation, wherein the land portion includes a plurality of first protrusions protruded away from the first passivation.

In one embodiment of the invention, a method for correcting a pattern placement on a substrate is disclosed. The method begins by detecting three reference points for a substrate. A plurality of sets of three die location points are detected, each set indicative of an orientation of a die structure, the plurality of sets include a first set associated with a first dies and a second set associated with a second die. A local transformation is calculated for the orientation of the first die and the second on the substrate. Three orientation points are selected from the plurality of sets of three die location points wherein the orientation points are not set members of the same die. A first global orientation of the substrate is calculated from the selected three points from the set of points and the first global transformation and the local transformation for the substrate are stored.