A semiconductor device includes an insulating layer, conductors, a semiconductor element and a sealing resin. The insulating layer has first and second surfaces opposite to each other in the thickness direction. Each conductor has an embedded part whose portion is embedded in the insulating layer and a redistribution part disposed at the second surface and connected to the embedded part. The semiconductor element has electrodes provided near the first surface and connected the embedded parts of the conductors. The semiconductor element is in contact with the first surface. The sealing resin partially covers the semiconductor element and is in contact with the first surface. The redistribution parts include portions outside the semiconductor element as viewed in the thickness direction. The insulating layer has grooves recessed from the second surface in the thickness direction. The redistribution parts are in contact with the grooves.

A semiconductor structure includes a semiconductor device, a conductive line, a dielectric layer and a redistribution layer (RDL). The conductive line is present over the semiconductor device. The dielectric layer is present over the conductive line. The RDL includes a conductive structure over the dielectric layer and a conductive via extending downwards from the conductive structure and through the dielectric layer. The conductive via comprises a bottom portion, a top portion, and a tapered portion between the bottom and top portions, wherein the tapered portion has a width variation greater than that of the bottom and top portions.

A method of forming a semiconductor structure includes the following steps. A dielectric layer is formed over a conductive line. A photoresist layer is formed over the dielectric layer. The photoresist layer is patterned to form a mask feature and an opening is defined by the mask feature. The opening has a bottom portion and a top portion communicated to the bottom portion, and the top portion is wider than the bottom portion. The dielectric layer is etched to form a via hole in the dielectric layer using the mask feature as an etch mask, such that the via hole has a bottom portion and a tapered portion over the bottom portion. The conductive material is filled in the via hole to form a conductive via.

Provided is a semiconductor device including a substrate, a passivation layer, and a connector. The passivation layer is disposed on the substrate. The connector is embedded in the passivation. An interface of the connector in contact with the passivation layer is uneven, thereby improving the structural stability of the connector. A method of manufacturing the semiconductor is also provided.

An integrated circuit (IC) device includes a redistribution line over a substrate, wherein an entire sidewall of the redistribution line is curved. The IC device further includes a passivation layer over the redistribution line, wherein a distance from a bottommost surface of the passivation layer to the substrate is less than a distance from a bottommost surface of the redistribution line to the substrate. The IC device further includes a polymer layer over the passivation layer.

This disclosure provides an integrated circuit device that includes a RDL that is interlocked with a bump (or “pillar”). The interlocked interface provides the contact RDL-bump interface with increased structural stability that can better withstand the thermal stresses associated with high performance devices IC devices. The interlock structure mitigates crack/delamination that occurs at the RDL-bump interface in large IC chips that are generally subjected to higher stresses during operation.

A semiconductor device includes: a lower structure; a redistribution insulating layer disposed over the lower structure; a redistribution conductive layer disposed over the redistribution insulating layer and electrically connected to a part of the lower structure, the redistribution conductive layer including a redistribution pad; and a protective layer covering the redistribution insulating layer and the redistribution conductive layer while leaving the redistribution pad exposed. The redistribution conductive layer includes a trench disposed adjacent to the redistribution pad, and a part of the protective layer fills the trench.

An electronic device package and a method for manufacturing the same are provided. The electronic device package includes a substrate, a conductive trace, a passivation layer and an upper wiring. The conductive trace is disposed over the substrate. The conductive trace includes a body portion disposed on the substrate, and a cap portion disposed on the body portion, and the cap portion is wider than the body portion. The passivation layer covers the conductive trace. The upper wiring is disposed on the passivation layer and electrically connected to the cap portion of the conductive trace through an opening of the passivation layer.

Provided is a semiconductor device including a substrate, a passivation layer, and a connector. The passivation layer is disposed on the substrate. The connector is embedded in the passivation. An interface of the connector in contact with the passivation layer is uneven, thereby improving the structural stability of the connector. A method of manufacturing the semiconductor is also provided.

Methods for forming dummy under-bump metallurgy structures and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a second passivation layer over the first passivation layer; a first under-bump metallurgy (UBM) structure over the first redistribution line, the first UBM structure extending through the first passivation layer and the second passivation layer and being electrically coupled to the first redistribution line; and a second UBM structure over the second redistribution line, the second UBM structure extending through the second passivation layer, the second UBM structure being electrically isolated from the second redistribution line by the first passivation layer.