A multi-chip package including a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first side having a first conductive layer, a second side having a second conductive layer, and an edge, the first conductive layer coupled to the second conductive layer at a location adjacent to the edge. The second integrated circuit is coupled to the second conductive layer of the first integrated circuit.

An object of the present invention is to provide a circular support substrate that allows for positioning based solely on its outer periphery shape. As a means for solving the problems, a circular support substrate is provided that has at least three chords along its circumference, wherein the chords are provided at positions where they do not run linearly symmetrical to the straight line passing through the center axis of the circular support substrate.

A package includes: an electronic component that includes a dielectric layer as a base and a semiconductor die attached on top of the dielectric layer, the semiconductor die having an active area with monolithically integrated circuit elements; and an encapsulant encapsulating the dielectric layer and the semiconductor die. The encapsulant is a mold compound having different material properties than the dielectric layer. A method of manufacturing package is also described.

The present technology relates to an imaging device, an electronic apparatus, and a method of manufacturing an imaging device capable of thinning a semiconductor on a terminal extraction surface while maintaining a strength of a semiconductor chip. There is provided an imaging device including: a first substrate having a pixel region in which pixels are two-dimensionally arranged, the pixels performing photoelectric conversion of light; and a second substrate in which a through silicon via is formed, in which a dug portion is formed in a back surface of the second substrate opposite to an incident side of light of the second substrate, and a redistribution layer (RDL) connected to a back surface of the first substrate is formed in the dug portion. The present technology can be applied to, for example, a semiconductor package including a semiconductor chip.

A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.

A semiconductor device has a semiconductor wafer and a first conductive layer formed over the semiconductor wafer as contact pads. A first insulating layer formed over the first conductive layer. A second conductive layer including an interconnect site is formed over the first conductive layer and first insulating layer. The second conductive layer is formed as a redistribution layer. A second insulating layer is formed over the second conductive layer. An opening is formed in the second insulating layer over the interconnect site. The opening extends to the first insulating layer in an area adjacent to the interconnect site. Alternatively, the opening extends partially through the second insulating layer in an area adjacent to the interconnect site. An interconnect structure is formed within the opening over the interconnect site and over a side surface of the second conductive layer. The semiconductor wafer is singulated into individual semiconductor die.

CTE compensation for wafer-level and chip-scale packages and assemblies.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first pad positioned above the substrate, and a first redistribution structure including a first redistribution conductive layer positioned on the first pad and a first redistribution thermal release layer positioned on the first redistribution conductive layer. The first redistribution thermal release layer is configured to sustain a thermal resistance between about 0.04° C. cm.sup.2/Watt and about 0.25° C. cm.sup.2/Watt.

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed over the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad, and the protection layer has a trench. The semiconductor device structure includes a conductive structure formed in the trench and on the protection layer. The conductive structure is electrically connected to the conductive pad, and the conductive structure has a concave top surface, and the lowest point of the concave top surface is higher than the top surface of the protection layer.

An antenna module includes an antenna substrate including an antenna pattern; a semiconductor package disposed on a lower surface of the antenna substrate, electrically connected to the antenna substrate, and having a semiconductor chip embedded therein; and an electronic component disposed at a side of the antenna substrate, electrically connected to the antenna substrate, and spaced apart from the semiconductor package by a predetermined distance. The antenna module includes a connection substrate connected to a portion of the antenna substrate, the connection substrate having an extension portion extending outward from the side of the antenna substrate, and the electronic component is disposed on the extension portion of the connection substrate to electrically connect to an inner wiring layer of the antenna substrate.