A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.

The semiconductor device has the CSP structure, and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad, and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps.

Implementations of image sensor packages may include an image sensor chip, a first layer including an opening therethrough coupled to a first side of the image sensor chip, and a optically transmissive cover coupled to the first layer. The optically transmissive cover, the first layer, and the image sensor chip may form a cavity within the image sensor. The image sensor package may also include at least one electrical contact coupled to a second side of the image sensor chip opposing the first side and an encapsulant coating an entirety of the sidewalls of the image sensor package.

A package module includes a connection structure including one or more redistribution layers, a semiconductor chip disposed on the connection structure and having a connection pad electrically connected to the one or more redistribution layers, a plurality of electronic components disposed on the connection structure and electrically connected to the one or more redistribution layers, one or more frames disposed on the connection structure, and an encapsulant disposed on the connection structure, and respectively covering at least portions of the semiconductor chip, the plurality of electronic components, and the one or more frames. At least a portion of an outer side surface of the encapsulant is coplanar on the same level as at least a portion of an outer side surface of at least one of the one or more frames.

A semiconductor device includes a semiconductor substrate, a passivation layer overlying the semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer is formed on the interconnect structure and has a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region.

A semiconductor package includes a frame having a wiring structure and having a recess portion, a semiconductor chip having an active surface with a connection pad disposed thereon and disposed in the recess portion, an encapsulant sealing the semiconductor chip, and a redistribution layer having a first via connected to the connection and a second via connected to a portion of the wiring structure. The semiconductor chip includes a protective insulating film disposed on the active surface and having an opening exposing a region of the connection pad, and a redistribution capping layer connected to the region of the connection pad and extending onto the protective insulating film, and a surface of the redistribution capping layer is substantially the same level as a surface of the portion of the wiring structure, exposed from the first surface.

A light-emitting package structure and a manufacturing method thereof are provided. The light-emitting package structure includes a driving device and at least one light-emitting chip. The driving device includes a driving chip and a redistribution layer structure formed over the driving chip. The driving chip has a first surface and a second surface opposite to the first surface. The redistribution layer structure includes a plurality of first conductive pads disposed on the first surface and a plurality of second conductive pads disposed on the second surface, and one of the first conductive pads is electrically connected to one of the second conductive pads. The at least one light-emitting chip is disposed on the first surface of the driving chip and electrically connected to the driving chip through the first conductive pads.

The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate, forming a first pad above the substrate, forming a first redistribution conductive layer on the first pad, and forming a first redistribution thermal release layer on the first redistribution conductive layer. The first redistribution conductive layer and the first redistribution thermal release layer together form a first redistribution structure and the first redistribution thermal release layer is configured to sustain a thermal resistance between about 0.04° C. cm.sup.2/Watt and about 0.25° C. cm.sup.2/Watt.

An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

A fan-out semiconductor package includes a first connection structure having first and second surfaces, a first semiconductor chip disposed on the first surface, a first encapsulant disposed on the first surface and covering at least a portion of the first semiconductor chip, a second semiconductor chip disposed on the second surface, one or more first metal members disposed on the second surface, one or more second metal members disposed on the second surface, a second encapsulant disposed on the second surface and respectively covering at least portions of the second semiconductor chip and the first and second metal members, and a second connection structure disposed on an opposite side of a side of the second encapsulant, on which the first connection structure is disposed.