A semiconductor device including a semiconductor die, an encapsulant and a redistribution structure is provided. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the semiconductor die and the encapsulant and is electrically connected to the semiconductor die. The redistribution structure includes a dielectric layer, a conductive via in the dielectric layer and a redistribution wiring covering the conductive via and a portion of the dielectric layer. The conductive via includes a pillar portion embedded in the dielectric layer and a protruding portion protruding from the pillar portion, wherein the protruding portion has a tapered sidewall.

A semiconductor package includes: a redistribution substrate; a frame including first and second vertical connection conductors, and having a through-hole; first and second semiconductor chips; an encapsulant; a second redistribution structure disposed on the encapsulant, a conductive wire electrically connecting the second semiconductor chip and the second vertical connection conductor; and a vertical connection via penetrating a portion of the encapsulant, and electrically connecting the second redistribution structure and the first vertical connection conductor. The first semiconductor chip is connected to the second vertical connection conductor by the first redistribution structure.

An embodiment is a package including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound and the chip and has a first opening exposing the contact pad. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer fills the first opening. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer and has a second opening over the first opening. A second metallization layer is formed overlying the second dielectric layer and formed in the second opening.

A package structure includes at least one semiconductor die, an insulating encapsulant and a redistribution structure. The at least one semiconductor die has a plurality of conductive posts, wherein a top surface of the plurality of conductive posts has a first roughness. The insulating encapsulant is encapsulating the at least one semiconductor die. The redistribution structure is disposed on the insulating encapsulant in a build-up direction and is electrically connected to the at least one semiconductor die. The redistribution structure includes a plurality of conductive via portions and a plurality of conductive body portions embedded in dielectric layers, wherein a top surface of the plurality of conductive body portions has a second roughness, and the second roughness is greater than the first roughness.

A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface disposed to oppose the active surface; a dummy chip disposed in the through-hole and spaced apart from the semiconductor chip; a second connection member disposed on the first connection member, the dummy chip, and the active surface of the semiconductor chip; and an encapsulant encapsulating at least portions of the first connection member, the dummy chip, and the inactive surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads.

An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.

A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, a heat dissipation element and conductive balls. The insulating encapsulant is encapsulating the semiconductor die, and has a first surface and a second surface opposite to the first surface. The first redistribution layer is located on the first surface of the insulating encapsulant and includes at least one feed line and one ground plate. The second redistribution layer is located on the second surface of the insulating encapsulant and electrically connected to the semiconductor die and the first redistribution layer. The heat dissipation element is disposed on the first redistribution layer and includes a conductive base and antenna patterns, wherein the antenna patterns is electrically connected to the feed line and is electrically coupled to the ground plate of the first redistribution layer.

The method of manufacturing a connection structure of a semiconductor chip includes: preparing a semiconductor chip having a first surface having a connection pad disposed thereon and a second surface opposing the first surface and including a passivation layer disposed on the first surface and covering the connection pad; forming an insulating layer on the first surface of the semiconductor chip, the insulating layer covering at least a portion of the passivation layer; forming a via hole penetrating through the insulating layer to expose at least a portion of the passivation layer; exposing at least a portion of the connection pad by removing the passivation layer exposed by the via hole; forming a redistribution via by filling the via hole with a conductive material; and forming a redistribution layer on the redistribution via and the insulating layer.

A semiconductor device package and a method for manufacturing the semiconductor device package are provided. The semiconductor device package includes a carrier, an electronic component, a first encapsulant and a conductive via. The carrier has a first surface and a second surface opposite to the first surface. The semiconductor device is mounted at the second surface of the carrier. The first encapsulant encapsulates the first surface of the carrier and has a surface facing away from the first surface of the carrier. The conductive via extends from the surface of the first encapsulant into the carrier.

A package structure includes a molding material, at least one through-via, at least one conductor, at least one dummy structure and an underfill. The through-via extends through the molding material. The conductor is present on the through-via. The dummy structure is present on the molding material and includes a dielectric material. The underfill is at least partially present between the conductor and the dummy structure.