A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate including a porous silicon (PSi) region resides over the top surface of the device region. Herein, the PSi region has a porosity between 1% and 80%. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.

A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.

A display device includes a display area comprising pixels, a fan-out area, a pad area, a display driver, a metal layer disposed on a substrate, a data line, a first voltage line, and a second voltage line extending in a first direction on the metal layer in the display area, a fan-out line electrically connecting the data line to the display driver on the metal layer in the fan-out area, a gate line disposed on the metal layer in the display area and extending in a second direction intersecting the first direction, a source-drain layer disposed on the gate line, and an electrode layer disposed on the source-drain layer. The first voltage line includes a first plate portion disposed on the source-drain layer in the fan-out area, and the second voltage line comprises a second plate portion disposed on the electrode layer in the fan-out area.

Processing methods may be performed to form a fan-out interconnect structure. The methods may include forming a semiconductor active device structure overlying a first substrate. The semiconductor active device structure may include first conductive contacts. The methods may include forming an interconnect structure overlying a second substrate. The interconnect structure may include second conductive contacts. The methods may also include joining the first substrate with the second substrate. The joining may include coupling the first conductive contacts with the second conductive contacts. The interconnect structure may extend beyond the lateral dimensions of the semiconductor active device structure.

Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

An electronic device package includes an encapsulated electronic component, a redistribution layer (RDL) and a conductive via. The RDL is disposed above the encapsulated electronic component. The RDL includes a circuit layer comprising a conductive pad including a pad portion having a curved edge and a center of curvature, and an extension portion protruding from the pad portion and having a curved edge and a center of curvature. The circuit layer further includes a dielectric layer above the RDL. The conductive via is disposed in the dielectric layer and connected to the conductive pad of the RDL. A center of the conductive via is closer to the center of curvature of the edge of the extension portion than to the center of curvature of the edge of the pad portion.

Various embodiments of fanout packages are disclosed. A method of forming a microelectronic assembly is disclosed. The method can include bonding a first surface of at least one microelectronic substrate to a surface of a carrier using a direct bonding technique without an intervening adhesive, the microelectronic substrate having a plurality of conductive interconnections on at least one surface of the microelectronic substrate. The method can include applying a molding material to an area of the surface of the carrier surrounding the microelectronic substrate to form a reconstituted substrate. The method can include processing the microelectronic substrate. The method can include singulating the reconstituted substrate at the area of the surface of the carrier and at the molding material to form the microelectronic assembly.

An IC chip includes I/O bumps on a back side, a first die, a second die, a first circuit, and a second circuit. The first die has driver circuits for LED devices, the LED devices being located on a front-facing surface of the first die. The first circuit extends from the front side toward the back side and across a thickness of the first die. The first circuit provides electrical connections between the LED devices and at least some of the I/O bumps. The first die and the second die can be stacked vertically or arranged laterally adjacent. The second circuit extends between the first die and the second die to electrically connect the first die and the second die. A circuit board can be electrically connected to the IC chip through the I/O bumps to, among other things, provide power to the various components of the IC chip.

A semiconductor package includes a semiconductor chip having at least one chip pad disposed on one surface thereof; a wiring pattern disposed on top of the semiconductor chip and having at least a portion thereof in contact with the chip pad to be electrically connected to the chip pad; and a solder bump disposed on outer surface of the wiring pattern to be electrically connected to the chip pad through the wiring pattern.