An optoelectronic device includes an optical integrated circuit having a first surface and a second surface opposite the first surface. The optical integrated circuit has an optical zone of the first surface of the optical integrated circuit. The device includes an electrically insulating material disposed over the optical integrated circuit, where he electrically insulating material partially covers the first surface so as to expose the optical zone.

Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A core layer and a dielectric layer are sequentially stacked over the package array. The core layer includes a plurality of cavities. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer having a core layer formed thereon is provided. The core layer includes a plurality of cavities penetrating through the core layer. The dielectric layer and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

A method of manufacture of an integrated circuit system includes: providing a semiconductor wafer with a bond pad; attaching a detachable carrier to the semiconductor wafer, the detachable carrier including a carrier frame portion and a terminal structure; removing the carrier frame portion with the terminal structure attached to the semiconductor wafer; and forming an encapsulation encapsulating the semiconductor wafer, the bond pad, and the terminal structure.

A method of fabricating a stretchable and flexible electronic device includes forming each of the functional layers is by: (i) forming on an elastomer substrate a conductive interconnect pattern having islands interconnected by bridges; (ii) applying a conductive paste to the islands; (iii) positioning at least one functional electronic component on each island; and (iv) applying heat to cause the conductive paste to reflow. An elastomer encapsulant is formed over the functional electronic components and the conductive interconnect pattern on each of the functional layers. The elastomer encapsulant has a Young's modulus equal to or less than that of the substrate. The encapsulant includes a pigment to increase absorption of laser light. At least one via is laser ablated, which provides electrical connection to any two functional layers. The via is filled with solder paste to create a bond and electrical connection between the functional layers.

Methods for forming an integrated device using CMOS processing with wafer bonding. In an embodiment, a method is disclosed that includes defining an integrated circuit function using a front-end substrate having one or more active devices and a back-end substrate having connections formed in metal layers in dielectric material, wherein the back-end substrate is free from active devices; manufacturing the front-end substrate in a first semiconductor process; more or less simultaneously, manufacturing the back-end substrate in a second semiconductor process; physically contacting bonding surfaces of the front-end substrate and the back-end substrate; and performing wafer bonding to form bonds between the front-end and back-end substrates to form an integrated circuit. Additional methods are disclosed.

The carrier-foil-attached ultra-thin copper foil according to one embodiment of the present invention comprises a carrier foil, a release layer, a first ultra-thin copper foil, an Al layer, and a second ultra-thin copper foil, wherein the release layer may comprise a first metal (A1) having peeling properties, and a second metal (B1) and third metal (C1) facilitating the plating of the first metal (A1).

A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer having a core layer formed thereon is provided. The core layer includes a plurality of cavities penetrating through the core layer. The dielectric layer and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.