A microelectronic device is formed by forming a platinum-containing layer on a substrate of the microelectronic device. A cap layer is formed on the platinum-containing layer so that an interface between the cap layer and the platinum-containing layer is free of platinum oxide. The cap layer is etchable in an etch solution which also etches the platinum-containing layer. The cap layer may be formed on the platinum-containing layer before platinum oxide forms on the platinum-containing layer. Alternatively, platinum oxide on the platinum-containing layer may be removed before forming the cap layer. The platinum-containing layer may be used to form platinum silicide. The platinum-containing layer may be patterned by forming a hard mask or masking platinum oxide on a portion of the top surface of the platinum-containing layer to block the wet etchant.

A method of manufacturing an array of planar wafer level metal posts includes plating an array of posts within a photoresist (PR) pattern mold on a substrate of a first wafer. Stripping the PR pattern mold from the substrate and array of posts. Applying an oxide layer, at a temperature of below 150 degrees Celsius, over a surface of the first wafer. Applying chemical-mechanical polishing (CMP) to planarize the oxide layer and the array of posts.

A method of fabricating an integrated circuit (IC) chip is disclosed. The method starts with opening a window on a first surface of the IC chip through a passivation overcoat to expose the copper metallization layer. The window has sidewalls and a bottom that is adjacent the copper metallization layer. The method continues with depositing a barrier conductive stack on the passivation overcoat and exposed portions of the copper metallization layer, then depositing a sacrificial conductive stack on the barrier conductive stack. The sacrificial conductive stack has a thickness between 50 and 500 . The first surface of the semiconductor chip is polished to remove the sacrificial conductive stack and the barrier conductive stack from the surface of the passivation overcoat.

A semiconductor device assembly that includes a first side of a semiconductor device supported on a substrate to permit the processing of a second side of the semiconductor device. A filler material deposited on the semiconductor device supports the semiconductor device on the substrate. The filler material does not adhere to the semiconductor device or the substrate. Alternatively, the filler material may be deposited on the substrate. Instead of a filler material, the substrate may include a topography configured to support the semiconductor device. Adhesive applied between an outer edge of the first side of the semiconductor and the substrate bonds the outer edge of the semiconductor device to the substrate to form a semiconductor device assembly. A second side of the semiconductor device may then be processed and the outer edge of the semiconductor device may be cut off to release the semiconductor device from the assembly.

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

A method of fabricating a contact hole and a fuse hole includes providing a dielectric layer. A conductive pad and a fuse are disposed within the dielectric layer. Then, a first mask is formed to cover the dielectric layer. Later, a first removing process is performed by taking the first mask as a mask to remove part the dielectric layer to form a first trench. The conductive pad is disposed directly under the first trench and does not expose through the first trench. Subsequently, the first mask is removed. After that, a second mask is formed to cover the dielectric layer. Then, a second removing process is performed to remove the dielectric layer directly under the first trench to form a contact hole and to remove the dielectric layer directly above the fuse by taking the second mask as a mask to form a fuse hole.

Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices.

Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices.

A semiconductor device assembly that includes a first side of a semiconductor device supported on a substrate to permit the processing of a second side of the semiconductor device. A filler material deposited on the semiconductor device supports the semiconductor device on the substrate. The filler material does not adhere to the semiconductor device or the substrate. Alternatively, the filler material may be deposited on the substrate. Instead of a filler material, the substrate may include a topography configured to support the semiconductor device. Adhesive applied between an outer edge of the first side of the semiconductor and the substrate bonds the outer edge of the semiconductor device to the substrate to form a semiconductor device assembly. A second side of the semiconductor device may then be processed and the outer edge of the semiconductor device may be cut off to release the semiconductor device from the assembly.

A method of fabricating a contact hole and a fuse hole includes providing a dielectric layer. A conductive pad and a fuse are disposed within the dielectric layer. Then, a first mask is formed to cover the dielectric layer. Later, a first removing process is performed by taking the first mask as a mask to remove part the dielectric layer to form a first trench. The conductive pad is disposed directly under the first trench and does not expose through the first trench. Subsequently, the first mask is removed. After that, a second mask is formed to cover the dielectric layer. Then, a second removing process is performed to remove the dielectric layer directly under the first trench to form a contact hole and to remove the dielectric layer directly above the fuse by taking the second mask as a mask to form a fuse hole.