A semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor device and a second semiconductor device are formed within a semiconductor wafer and a scribe region between the first semiconductor device and the second semiconductor device is patterned. A singulation process is then utilized within the scribe region to singulate the first semiconductor device from the second semiconductor device. The first semiconductor device and the second semiconductor device are then bonded to a second semiconductor substrate and thinned in order to remove extension regions from the first semiconductor device and the second semiconductor device.

A method of manufacturing a bond pad structure may include depositing an aluminum-copper (AlCu) layer over a dielectric layer; and depositing an aluminum-chromium (AlCr) layer directly over the AlCu layer.

Representative implementations of devices and techniques provide a temporary access point (e.g., for testing, programming, etc.) for a targeted interconnect located among multiple finely spaced interconnects on a surface of a microelectronic component. One or more sacrificial layers are disposed on the surface of the microelectronic component, overlaying the multiple interconnects. An insulating layer is disposed between a conductive layer and the surface, and includes a conductive via through the insulating layer that electrically couples the conductive layer to the target interconnect. The sacrificial layers are configured to be removed after the target interconnect has been accessed, without damaging the surface of the microelectronic component.

A semiconductor device includes a substrate, a wiring formed on the substrate, an anti-reflection film of titanium nitride formed on the wiring, and a silicon oxide film formed on the anti-reflection film. A pad portion which exposes the wiring is formed at a place where a first opening portion and a second opening portion overlap with each other. A metal nitride region containing fewer dangling bonds is formed from a metal nitride film containing fewer dangling bonds than in the anti-reflection film in at least a part of one or both of an opposed surface of the anti-reflection film which faces the silicon oxide film above the anti-reflection film, and an exposed surface of the anti-reflection film which is exposed in the second opening portion.

Capacitive coupling of integrated circuit die components and other conductive areas is provided. Each component to be coupled has a surface that includes at least one conductive area, such as a metal pad or plate. An ultrathin layer of dielectric is formed on at least one surface to be coupled. When the two components, e.g., one from each die, are permanently contacted together, the ultrathin layer of dielectric remains between the two surfaces, forming a capacitor or capacitive interface between the conductive areas of each respective component. The ultrathin layer of dielectric may be composed of multiple layers of various dielectrics, but in one implementation, the overall thickness is less than approximately 50 nanometers. The capacitance per unit area of the capacitive interface formed depends on the particular dielectric constants of the dielectric materials employed in the ultrathin layer and their respective thicknesses. Electrical and grounding connections can be made at the edge of the coupled stack.

A method of fabricating a contact hole and a fuse hole includes providing a dielectric layer. A conductive pad and a fuse are disposed within the dielectric layer. Then, a first mask is formed to cover the dielectric layer. Later, a first removing process is performed by taking the first mask as a mask to remove part the dielectric layer to form a first trench. The conductive pad is disposed directly under the first trench and does not expose through the first trench. Subsequently, the first mask is removed. After that, a second mask is formed to cover the dielectric layer. Then, a second removing process is performed to remove the dielectric layer directly under the first trench to form a contact hole and to remove the dielectric layer directly above the fuse by taking the second mask as a mask to form a fuse hole.

A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

A microelectronic device is formed by forming a platinum-containing layer on a substrate of the microelectronic device. A cap layer is formed on the platinum-containing layer so that an interface between the cap layer and the platinum-containing layer is free of platinum oxide. The cap layer is etchable in an etch solution which also etches the platinum-containing layer. The cap layer may be formed on the platinum-containing layer before platinum oxide forms on the platinum-containing layer. Alternatively, platinum oxide on the platinum-containing layer may be removed before forming the cap layer. The platinum-containing layer may be used to form platinum silicide. The platinum-containing layer may be patterned by forming a hard mask or masking platinum oxide on a portion of the top surface of the platinum-containing layer to block the wet etchant.

A method of manufacturing a wafer assembly includes forming an array of planar wafer level metal posts extending from a surface of a substrate of a first wafer. After forming the array of posts, an oxide layer is applied over the surface of the first wafer and around the array of posts, the oxide layer being applied at a temperature of below 150 degrees Celsius.