H01L2224/03013

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
20240387422 · 2024-11-21 ·

A semiconductor structure is provided. The semiconductor structure includes an interconnection structure, a passivation layer and a dielectric capping layer. The interconnect structure has a conductive pad located at a top of the interconnection structure. The passivation layer is disposed on the interconnection structure. The passivation layer has a first opening to expose a portion of the conductive pad. The dielectric capping layer is conformally formed on the passivation layer and extends into the first opening. The dielectric capping layer has a second opening to expose the portion of the conductive pad.

BONDING STRUCTURES OF INTEGRATED CIRCUIT DEVICES AND METHOD FORMING THE SAME
20240371804 · 2024-11-07 ·

A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.

Bond Features For Reducing Non-Bond and Methods of Forming the Same
20250006677 · 2025-01-02 ·

A method includes depositing a first dielectric layer as a first surface layer of a first package component, forming a plurality of metal pads in the first dielectric layer, depositing a second dielectric layer as a second surface layer of a second package component, and bonding the second package component to the first package component. The first dielectric layer is bonded to the second dielectric layer. At a time after the bonding, a metal pad in the plurality of metal pads has a top surface contacting a bottom surface of the second dielectric layer.

Method for Packaging Stacking Flip Chip

The present application is applicable to the field of semiconductor technology and provides a method for packaging stacking a flip chip, which includes: placing a filling template on a substrate, the filling template being provided with a through hole of a preset pattern; filling a filling material into the through hole of the filling template, and after the filling material being formed on the substrate, removing the filling template; placing a chip with solder balls on the substrate formed with the filling material, such that at least a portion of the solder balls being covered by the filling material; and connecting the chip to the substrate through the solder balls, and curing the filling material with air gaps formed between the at least a portion of the solder balls covered with the filling material.

UNDER-BUMP METALLIZATION STRUCTURES AND ASSOCIATED METHODS OF FORMATION
20250022820 · 2025-01-16 ·

Methods, systems, and devices for semiconductor manufacturing are described. One such method includes forming a first layer comprising a first material. A top surface of the first layer extends along a first direction and a second direction. In some cases, the method includes forming, on at least the top surface of the first layer, a second layer comprising a second material, and forming a void in the second layer. Forming the void may expose a portion of the top surface of the first layer. In some cases, the method may include forming one or more layers on a top surface of the second layer and on the exposed portion of the top surface of the first layer. The method may also include performing a material removal operation that lifts portions of the one or more layers formed on the top surface of the second layer off of the top surface.

COLLARS FOR UNDER-BUMP METAL STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS

The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

Interconnect structures for fine pitch assembly of semiconductor structures and related techniques

A semiconductor structure includes a substrate having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes one or more interconnect pads having first and second opposing surfaces and one or more sides. The first surface of each one of the interconnect pads is disposed over or beneath select portions of at least the second surface of the substrate and is electrically coupled to select ones of the plurality of electrical connections. The semiconductor structure additionally includes an isolating layer having first and second opposing surfaces and openings formed in select portions of the isolating layer extending between the second surface of the isolating layer and the second surfaces of the interconnect pads. A corresponding method for fabricating a semiconductor structure is also provided.

Collars for under-bump metal structures and associated systems and methods

The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

Waterfall wire bonding

A wire bonded structure for a semiconductor device is disclosed. The wire bonded structure comprises a bonding pad; and a continuous length of wire mutually diffused with the bonding pad, the wire electrically coupling the bonding pad with a first electrical contact and a second electrical contact different from the first electrical contact.

Waterfall wire bonding

A wire bonded structure for a semiconductor device is disclosed. The wire bonded structure comprises a bonding pad; and a continuous length of wire mutually diffused with the bonding pad, the wire electrically coupling the bonding pad with a first electrical contact and a second electrical contact different from the first electrical contact.