An embodiment semiconductor structure includes a metal layer. The semiconductor structure also includes a redistribution layer (RDL) structure including an RDL platform and a plurality of RDL pillars disposed between the RDL platform and the metal layer. Additionally, the semiconductor structure includes an under-bump metal (UBM) layer disposed on the RDL platform and a solder bump disposed on the UBM layer, where the UBM layer, the RDL platform, and the RDL pillars form an electrical connection between the solder bump and the metal layer.

A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, one or more contacts located on the major surface and an encapsulant covering at least the major surface. A peripheral edge of each contact defines a contact area on the major surface. The device also includes one or more bond pads located outside the encapsulant. Each bond pad is electrically connected to a respective contact located on the major surface of the substrate by a respective metal filled via that passes through the encapsulant. A sidewall of each respective metal filled via, at the point at which it meets the respective contact, falls inside the contact area defined by the respective contact when viewed from above the major surface of the substrate, whereby none of the metal filling each respective via extends outside the contact area of each respective contact.

A semiconductor structure includes a substrate having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes one or more interconnect pads having first and second opposing surfaces and one or more sides. The first surface of each one of the interconnect pads is disposed over or beneath select portions of at least the second surface of the substrate and is electrically coupled to select ones of the plurality of electrical connections. The semiconductor structure additionally includes an isolating layer having first and second opposing surfaces and openings formed in select portions of the isolating layer extending between the second surface of the isolating layer and the second surfaces of the interconnect pads. A corresponding method for fabricating a semiconductor structure is also provided.

The invention relates to a power semiconductor chip (10) having at least one upper-sided potential surface and contacting thick wires (50) or strips, comprising a connecting layer (I) on the potential surfaces, and at least one metal molded body (24, 25) on the connecting layer(s), the lower flat side thereof facing the potential surface being provided with a coating to be applied to the connecting layer (I) according to a connection method, and the material composition thereof and the thickness of the related thick wires (50) or strips arranged on the upper side of the molded body used according to the method for contacting are selected corresponding to the magnitude.

The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

A semiconductor die includes a semiconductor surface including circuitry electrically connected to top-level bond pads exposed on a top surface of the semiconductor die, the top-level bond pads including inner bond pads and outer bond pads positioned beyond the inner bond pads. There is solder on at least the inner bond pads. A ring structure is positioned around a location of at least the inner bond pads.

The present application is applicable to the field of semiconductor technology and provides a method for packaging stacking a flip chip, which includes: placing a filling template on a substrate, the filling template being provided with a through hole of a preset pattern; filling a filling material into the through hole of the filling template, and after the filling material being formed on the substrate, removing the filling template; placing a chip with solder balls on the substrate formed with the filling material, such that at least a portion of the solder balls being covered by the filling material; and connecting the chip to the substrate through the solder balls, and curing the filling material with air gaps formed between the at least a portion of the solder balls covered with the filling material.

A display backboard and a manufacturing method thereof, and a display device are provided. The display backboard includes: a driving substrate; a plurality of driving electrodes on the driving substrate; and a plurality of connection structures respectively on the plurality of driving electrodes. The connection structure includes: at least one conductive component on the driving electrode; and a restriction component on a side of the driving electrodes provided with the at least one conductive component and in at least a part of a peripheral region of the at least one conductive component. The restriction component protrudes from the driving electrode and has a first height in a direction perpendicular to the driving substrate.

A display backboard and a manufacturing method thereof, and a display device are provided. The display backboard includes: a driving substrate; a plurality of driving electrodes on the driving substrate; and a plurality of connection structures respectively on the plurality of driving electrodes. The connection structure includes: at least one conductive component on the driving electrode; and a restriction component on a side of the driving electrodes provided with the at least one conductive component and in at least a part of a peripheral region of the at least one conductive component. The restriction component protrudes from the driving electrode and has a first height in a direction perpendicular to the driving substrate.

An integrated circuit has corner regions and non-corner regions between the corner regions and includes a semiconductor substrate, conductive pads, passivation layer, post-passivation layer, first conductive posts, and second conductive posts. The conductive pads are disposed over the semiconductor substrate. The passivation layer and the post-passivation layer are sequentially disposed over the conductive pads. The first conductive posts and the second conductive posts are disposed on the post-passivation layer and are electrically connected to the conductive pads. The first conductive posts are disposed in the corner regions and the second conductive posts are disposed in the non-corner regions. Each of the first conductive posts has a body portion and a protruding portion connected to the body portion. A central axis of the body portion of the first conductive post has an offset from a central axis of the protruding portion of the first conductive post.