In a semiconductor package in which a semiconductor substrate is mounted, thermal resistance of the semiconductor substrate is reduced. The semiconductor package includes a semiconductor substrate, an insulating layer, a metal layer, an interposer substrate, a mounting substrate, a signal transmission solder ball, and a solder member. A pad is provided on one surface of the semiconductor substrate. A different surface of the semiconductor substrate is covered with the insulating layer. The metal layer covers the insulating layer. A wire to be connected to the pad is formed on the interposer substrate. The signal transmission solder ball is jointed to the wire and the mounting substrate, and transmits a predetermined electrical signal. The solder member is jointed to the metal layer and the mounting substrate.

According to certain aspects, a packaging substrate can include a plurality of layers including an outer layer, and one or more components on a surface of the outer layer. The one or more components can include a radio-frequency circuit, where the radio-frequency circuit is covered by a protective coating configured to reduce surface roughness of the outer layer and not covered by solder resist.

A semiconductor device includes a substrate, a wiring formed on the substrate, an anti-reflection film of titanium nitride formed on the wiring, and a silicon oxide film formed on the anti-reflection film. A pad portion which exposes the wiring is formed at a place where a first opening portion and a second opening portion overlap with each other. A metal nitride region containing fewer dangling bonds is formed from a metal nitride film containing fewer dangling bonds than in the anti-reflection film in at least a part of one or both of an opposed surface of the anti-reflection film which faces the silicon oxide film above the anti-reflection film, and an exposed surface of the anti-reflection film which is exposed in the second opening portion.

Provided is a semiconductor device that is resistant to the corrosion of titanium nitride forming an anti-reflection film. The semiconductor device includes: a wiring layer which includes a wiring film made of aluminum or an aluminum alloy and formed on a substrate and a titanium nitride film formed on the wiring film; a protection layer which covers a top surface and a side surface of the wiring layer; and a pad portion which penetrates the protection layer and the titanium nitride film, and which exposes the wiring film, the protection layer including a first silicon nitride film, an oxide film, and a second silicon nitride film which are layered in the stated order from the side of the wiring layer.

A semiconductor device includes a substrate; a laminate which is formed on one main surface side of the substrate, and includes an aluminum alloy wiring and an insulating film surrounding the aluminum alloy wiring; and a silicon nitride film covering the laminate, in which the silicon nitride film and the insulating film have an opening portion, through which the silicon nitride film and the insulating film, formed at a position overlapped with a bonding portion of the aluminum alloy wiring, and a deposition made of a residue caused by reverse sputtering, which contains silicon and nitrogen, adheres to a portion exposed from the opening portion of a surface of the aluminum alloy wiring, to form a film.

A semiconductor device includes a first body having a first coefficient of thermal expansion (CTE) and a first surface, a third body having a third CTE and a third surface facing the first surface, and a fourth surface at an angle with respect to the third surface defining an edge of the third body, and a second body having a second CTE higher than the first and the third CTE, the second body contacting the first and the third surfaces. A post having a fourth CTE lower than the second CTE, transects the second body and contacts the edge.

A method of fabricating a contact hole and a fuse hole includes providing a dielectric layer. A conductive pad and a fuse are disposed within the dielectric layer. Then, a first mask is formed to cover the dielectric layer. Later, a first removing process is performed by taking the first mask as a mask to remove part the dielectric layer to form a first trench. The conductive pad is disposed directly under the first trench and does not expose through the first trench. Subsequently, the first mask is removed. After that, a second mask is formed to cover the dielectric layer. Then, a second removing process is performed to remove the dielectric layer directly under the first trench to form a contact hole and to remove the dielectric layer directly above the fuse by taking the second mask as a mask to form a fuse hole.

A semiconductor device comprises a metallization layer, a passivation layer disposed above the metallization layer, a copper redistribution layer disposed on the passivation layer, a second passivation layer disposed on the copper redistribution layer, and a polyimide layer disposed over the second passivation layer. The polyimide layer and the second passivation layer include a continuous gap there-through that exposes a portion of the copper redistribution layer.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an interconnect structure over a substrate. The interconnect structure includes a plurality of interconnects disposed within a dielectric structure. A bond pad structure is over the interconnect structure, a first masking layer is over the bond pad structure, and a second masking layer is over the first masking layer. The second masking layer contacts opposing outermost sidewalls of the bond pad structure and the first masking layer. A conductive bump vertically extends through the first masking layer and the second masking layer to contact the bond pad structure.

A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.