A bonding structure for connecting a chip and a metal material, and a manufacturing method thereof are provided. The bonding structure includes a substrate, a chip, a metal member, at least one metal wire and an alloy connection layer. An upper surface of the substrate has a first metal pad and a second metal pad. The chip is disposed on the first metal pad. The metal member is disposed above the chip. The at least one metal wire has a first end and a second end, the first end is connected to an upper surface of the metal piece, and the second end is connected to the second metal pad. The alloy connection layer is connected between the metal member and the chip, and covers at least a part of a lower surface of the metal member.

A semiconductor memory device and front-end method of fabricating nickel plated caps over bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication. In some examples, the method and device include one or more conductive and insulating layers formed over a substrate, and a plurality of memory cells over the conductive and insulating layers.

A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces.

A nanowire bonding interconnect for fine-pitch microelectronics is provided. Vertical nanowires created on conductive pads provide a debris-tolerant bonding layer for making direct metal bonds between opposing pads or vias. Nanowires may be grown from a nanoporous medium with a height between 200-1000 nanometers and a height-to-diameter aspect ratio that enables the nanowires to partially collapse against the opposing conductive pads, creating contact pressure for nanowires to direct-bond to opposing pads. Nanowires may have diameters less than 200 nanometers and spacing less than 1 m from each other to enable contact or direct-bonding between pads and vias with diameters under 5 m at very fine pitch. The nanowire bonding interconnects may be used with or without tinning, solders, or adhesives. A nanowire forming technique creates a nanoporous layer on conductive pads, creates nanowires within pores of the nanoporous layer, and removes at least part of the nanoporous layer to reveal a layer of nanowires less than 1 m in height for direct bonding.

Various embodiments of an integrated circuit (IC) die package are disclosed. An IC die package includes an IC die, an interposer structure electrically connected to the IC die, a first bonding structure, and a second bonding structure. The first bonding structure includes a first dielectric layer disposed on the IC die and also includes a first conductive pad having an embedded portion disposed in the first dielectric layer and an anchor portion extending over a top surface of the first dielectric layer. The second bonding structure includes a second dielectric layer disposed on the interposer structure, a second conductive pad disposed in the second dielectric layer, and an anchor layer surrounding the anchor portion.

A method for forming conductive structures between two substrates is disclosed. The method comprises: forming a first patterned base layer and a second patterned base layer on a first substrate and a second substrate, wherein the first and second patterned base layers comprise through-holes; forming first and second metallic contact structures in the through holes of the first and second patterned base layer, wherein both the first and second metallic contact structures have front surfaces that are higher than respective front surfaces of the first and second patterned base layers; forming a first and a second patterned polymer layer on the respective front surfaces of the first and second patterned base layer, wherein the first and second metallic contact structures are exposed from and higher than respective front surfaces of the first and second patterned polymer layer; passivating the front surfaces of the first and second metallic contact structures; bonding the front surfaces of the first and second metallic contact structures with each other; and bonding the front surfaces of the first and second patterned polymer layers with each other after the front surfaces of the first and second metallic contact structures are bonded with each other.

An element is disclosed. The element can include a non-conductive structure having a non-conductive bonding surface, a cavity at least partially extending through a portion of a thickness of the non-conductive structure from the non-conductive bonding surface, and a conductive pad disposed in the cavity. The cavity has a bottom side and a sidewall. The conductive pad has a bonding surface and a back side opposite the bonding surface. An average size of the grains at the bonding surface is smaller than an average size of the grains adjacent the bottom side of the cavity. The conductive pad can include a crystal structure with grains oriented along a 111 crystal plane. The element can be bonded to another element to form a bonded structure. The element and the other element can be directly bonded to one another without an intervening adhesive.

A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.

A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.

A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.