A semiconductor package includes a chip including a pad; a first insulation pattern on the chip and exposing the pad; a redistribution layer (RDL) on an upper surface of the first insulation pattern and connected to the pad; a second insulation pattern on the upper surface of the first insulation pattern and including an opening exposing a ball land of the RDL and a patterned portion in the opening; an under bump metal (UBM) on upper surfaces of the second insulation pattern and patterned portion and filling the opening, the UBM including a first locking hole exposing an edge of an upper surface of the ball land; and a conductive ball on an upper surface of the UBM and including a first locking portion in the first locking hole. The first locking hole may be about 10% to about 50% of the area of the UBM upper surface.

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

A method for manufacturing electronic chips includes forming, on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed beforehand, metallizations coupling contacts of adjacent integrated circuits to one another. The method further includes forming, on the side of the first face of the substrate, first trenches extending through the first face of the substrate and laterally separating the adjacent integrated circuits. The first trenches extend through the metallizations to form at least a portion of metallizations at each of the adjacent circuits.

A method for manufacturing electronic chips includes forming, on a side of an upper face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed, trenches laterally separating the integrated circuits. At least one metal connection pillar per integrated circuit is deposited on the side of the upper face of the substrate, and a protective resin extends in the trenches and on an upper face of the integrated circuits. The method further includes forming, from an upper face of the protective resin, openings located across from the trenches and extending over a width greater than or equal to that of the trenches, so as to clear a flank of at least one metal pillar of each integrated circuit. The integrated circuits are separated into individual chips by cutting.

A method for manufacturing electronic chips includes depositing, on a side of an upper face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed, a protective resin. The method includes forming, in the protective resin, at least one cavity per integrated circuit, in contact with an upper face of the integrated circuit. Metal connection pillars are formed by filling the cavities with metal. The integrated circuits are separated into individual chips by cutting the protective resin along cut lines extending between the metal connection pillars.

The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.

A semiconductor device includes a semiconductor substrate, a conductive pad disposed on the semiconductor substrate, and a pillar pattern disposed on the conductive pad. The semiconductor device further includes a solder seed pattern disposed on the pillar pattern, and a solder portion disposed on the pillar pattern and the solder seed pattern. A first width of the solder seed pattern is less than a second width of a top surface of the pillar pattern.

Patterning methods for forming patterned device substrates are provided. Also provided are devices made using the methods. The methods utilize photoresist features have re-entrant profiles to form a secondary metal hard mask that can be used to pattern an underlying device substrate.

A semiconductor structure includes a first passivation layer disposed over a metal line, a copper-containing RDL disposed over the first passivation layer, where the copper-containing RDL is electrically coupled to the metal line and where a portion of the copper-containing RDL in contact with a top surface of the first passivation layer forms an acute angle, and a second passivation layer disposed over the copper-containing RDL, where an interface between the second passivation layer and a top surface of the copper-containing RDL is curved. The semiconductor structure may further include a polymeric layer disposed over the second passivation layer, where a portion of the polymeric layer extends to contact the copper-containing RDL, a bump electrically coupled to the copper-containing RDL, and a solder layer disposed over the bump.

A semiconductor device package includes a connection structure having a first portion and a second portion extending from the first portion, the second portion having a width less than the first portion; and a dielectric layer surrounding the connection structure, wherein the dielectric layer and the second portion of the connection structure defines a space.