A device package includes a die, fan-out redistribution layers (RDLs) over the die, and an under bump metallurgy (UBM) over the fan-out RDLs. The UBM comprises a conductive pad portion and a trench encircling the conductive pad portion. The device package further includes a connector disposed on the conductive pad portion of the UBM. The fan-out RDLs electrically connect the connector and the UBM to the die.

Electroplating methods enable the plating of photoresist defined features which have substantially uniform morphology. The electroplating methods include copper electroplating baths with reaction products of pyridyl alkylamines and bisepoxides to electroplate the photoresist defined features. Such features include pillars, bond pads and line space features.

A method for making and a semiconductor device comprises a silicon die including a metal contact region and, at least one passivation layer covering the semiconductor die and patterned such as to form an opening to the metal contact region of the semiconductor die. A continuous part of a contact layer comprises a refractory metal, and overlaps and completely covers the opening in the at least one passivation layer to contact the metal contact region in the opening and adhere to the at least one passivation layer along the entire edge of the continuous part. The contact layer comprises at least an adhesion layer and at least a diffusion barrier layer. A noble metal layer is arranged over the contact layer and completely covers the continuous part to adhere to the at least one passivation layer around the edge of the continuous part.

A sensor device for use in harsh media, comprising a silicon die comprises a lowly doped region, and a contact layer, contacting the silicon die. The contact layer comprises a refractory metal and an ohmic contact to the silicon die via a silicide of the refractory metal. A noble metal layer is provided over the contact layer such that the contact layer is completely covered by the noble metal layer. The noble metal layer comprises palladium, platinum or a metal alloy of palladium and/or platinum. The noble metal layer is patterned to form an interconnect structure and a contact connecting via the contact layer to the ohmic contact. The noble metal layer is adapted for providing a shield to prevent modulation of the lowly doped region by surface charges. The noble metal layer may advantageously protect the contact layer against harsh media in an external environment of the sensor device.

A semiconductor device includes a first body having a first coefficient of thermal expansion (CTE) and a first surface, a third body having a third CTE and a third surface facing the first surface, and a fourth surface at an angle with respect to the third surface defining an edge of the third body, and a second body having a second CTE higher than the first and the third CTE, the second body contacting the first and the third surfaces. A post having a fourth CTE lower than the second CTE, transects the second body and contacts the edge.

A semiconductor device includes a substrate main body, a plurality of first bump pads, and redistribution layer (RDL). The first bump pads are disposed adjacent to a surface of the substrate main body, each of the first bump pads has a first profile from a top view, the first profile has a first width along a first direction and a second width along a second direction perpendicular to the first direction, and the first width of the first profile is greater than the second width of the first profile. The RDL is disposed adjacent to the surface of the substrate main body, and the RDL includes a first portion disposed between two first bump pads.

A semiconductor light-emitting device includes a light-emitting structure including a first semiconductor layer, an active layer and a second semiconductor layer sequentially stacked. A connection electrode is positioned above the light-emitting structure. The connection electrode includes a connection metal layer electrically connected to at least one of the first and second semiconductor layers. A UBM pattern is on the connection electrode. A connection terminal is on the UBM pattern. The connection metal layer includes a first metal element. A heat conductivity of the first metal element is higher than that of gold (Au). The connection terminal includes a second metal element. A first reactivity of the first metal element with the second metal element is lower than a second reactivity of gold (Au) with the second metal element.

The invention disclosed a method for manufacturing an electrode of a semiconductor device, comprising: forming a first interlayer dielectric layer having a first opening on a first surface of a semiconductor substrate; forming a first resist mask having a second opening on a surface of the first interlayer dielectric layer, wherein the first opening and the second opening are connected to form a first stacked opening; forming a first conductive layer on the first resist mask, wherein the first conductive layer comprises a first portion being located on a surface of the first resist mask and a second portion being located inside the first stacked opening; and removing the first resist mask, wherein the first portion of the first conductive layer is removed together with the first resist mask, and the second portion of the first conductive layer is retained as a first surface electrode.

Electroplating methods enable the plating of photoresist defined features which have substantially uniform morphology. The electroplating methods include copper electroplating baths with reaction products of -amino acids and bisepoxides to electroplate the photoresist defined features. Such features include pillars, bond pads and line space features.

A method of fabricating a thin film transistor structure is described. The method forms a photoresist pattern layer on an active pattern layer and a part of a gate insulating layer to expose a source predetermining position and a drain predetermining position of the gate insulating layer. The photoresist pattern layer has a plurality of inverted trapezoidal blocks which can be used as a mask, thereby depositing a metal layer on the photoresist pattern layer, the source predetermining position and the drain predetermining position. After removing the photoresist pattern layer and the metal layer thereon, the remaining metal layer is patterned to form a source and a drain. In the method of fabricating a thin film transistor structure, a fabricating process can be simplified, and it is unnecessary to form an etching stop layer to protect a back channel.