A semiconductor device is provided that can minimize the occurrence of poor joining between a copper electrode and a copper wire. The semiconductor device includes a semiconductor substrate; a copper electrode layer formed on the semiconductor substrate; a metallic thin-film layer formed on the copper electrode layer for preventing oxidation of the copper electrode layer, the metallic thin-film layer having an opening through which the copper electrode layer is exposed, the opening being located on an inner side relative to an outer periphery of the metallic thin-film layer; and an interconnection member containing copper as a main component, the interconnection member including a joining region covering the opening, the interconnection member being joined to the metallic thin-film layer and joined to the copper electrode layer in the opening.

Provided is a redistribution layer (RDL) structure including a substrate, a pad, a dielectric layer, a self-aligned structure, a conductive layer, and a conductive connector. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The self-aligned structure is disposed on the dielectric layer. The conductive layer extends from the pad to conformally cover a surface of the self-aligned structure. The conductive connector is disposed on the self-aligned structure. A method of manufacturing the RDL structure is also provided.

In described examples of an integrated circuit (IC) there is a substrate of semiconductor material having a first region with a first transistor formed therein and a second region with a second transistor formed therein. An isolation trench extends through the substrate and separates the first region of the substrate from the second region of the substrate. An interconnect region having layers of dielectric is disposed on a top surface of the substrate. A dielectric polymer is disposed in the isolation trench and in a layer over the backside surface of the substrate. An edge of the polymer layer is separated from the perimeter edge of the substrate by a space.

A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.

A method of manufacture of an integrated circuit system includes: providing a semiconductor wafer with a bond pad; attaching a detachable carrier to the semiconductor wafer, the detachable carrier including a carrier frame portion and a terminal structure; removing the carrier frame portion with the terminal structure attached to the semiconductor wafer; and forming an encapsulation encapsulating the semiconductor wafer, the bond pad, and the terminal structure.

A bonding pad layer system is deposited on a semiconductor chip as a base, for example, a micromechanical semiconductor chip, in which at least one self-supporting dielectric membrane made up of dielectric layers, a platinum conductor track and a heater made of platinum is integrated. In the process, the deposition of a tantalum layer takes place first, upon that the deposition of a first platinum layer, upon that the deposition of a tantalum nitride layer, upon that the deposition of a second platinum layer and upon that the deposition of a gold layer, at least one bonding pad for connecting with a bonding wire being formed in the gold layer. The bonding pad is situated in the area of the contact hole on the semiconductor chip, in which a platinum conductor track leading to the heater is connected using a ring contact and/or is connected outside this area.

The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 510.sup.6/ C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

Provided is a semiconductor device in which, in a case where a metallic plate (a conductive member) is bonded by being sintered to a semiconductor chip having an IGBT gate structure, an excess stress is less likely to be generated in a gate wiring section of the semiconductor chip even when pressure is applied in a sinter bonding process, so that a characteristic failure is reduced. The semiconductor device according to the present invention is characterized by: being provided with a semiconductor chip having a gate structure represented by an IGBT; including first gate wiring and second gate wiring formed on the surface of the semiconductor chip; and including an emitter electrode disposed so as to cover the first gate wiring and a sintered layer disposed above the emitter electrode, wherein a multilayer structure formed by including at least the emitter electrode and the sintered layer on the surface of the semiconductor chip continuously exists over a range including an emitter electrode connecting contact and gate wiring regions.

Provided is a semiconductor device in which, in a case where a metallic plate (a conductive member) is bonded by being sintered to a semiconductor chip having an IGBT gate structure, an excess stress is less likely to be generated in a gate wiring section of the semiconductor chip even when pressure is applied in a sinter bonding process, so that a characteristic failure is reduced. The semiconductor device according to the present invention is characterized by: being provided with a semiconductor chip having a gate structure represented by an IGBT; including first gate wiring and second gate wiring formed on the surface of the semiconductor chip; and including an emitter electrode disposed so as to cover the first gate wiring and a sintered layer disposed above the emitter electrode, wherein a multilayer structure formed by including at least the emitter electrode and the sintered layer on the surface of the semiconductor chip continuously exists over a range including an emitter electrode connecting contact and gate wiring regions.

A sintering powder comprising copper particles, wherein: the particles are at least partially coated with a capping agent, and the particles exhibit a D10 of greater than or equal to 100 nm and a D90 of less than or equal to 2000 nm.