Bonded wafer device structures, such as a wafer-on-wafer (WoW) structures, and methods of fabricating bonded wafer device structures, including an array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure. The array of contact pads formed in an interconnect level of at least one wafer may have an array pattern that corresponds to an array pattern of contact pads that is subsequently formed over a surface of the bonded wafer structure. The array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure may enable improved testing of individual wafers, including circuit probe testing, prior to the wafer being stacked and bonded to one or more additional wafers to form a bonded wafer structure.

A method of forming a semiconductor device with a metal pillar overlapping a first top metal interconnect and a second top metal interconnect is disclosed. The metal pillar overlapping the first top metal interconnect and second top metal interconnect is connected to the first top metal interconnect by top metal vias while the second top metal interconnect does not contain top metal vias and remains free of a direct electrical connection to the metal pillar. The metal pillars are attached directly to top metal vias without a bond pad of metal. The elimination of the bond pad layer reduces the mask count, processing, and cost of the device. In addition, the elimination of the bond pad results in reduced die area requirements for the metal pillar.

A method of forming a semiconductor device with a metal pillar overlapping a first top metal interconnect and a second top metal interconnect is disclosed. The metal pillar overlapping the first top metal interconnect and second top metal interconnect is connected to the first top metal interconnect by top metal vias while the second top metal interconnect does not contain top metal vias and remains free of a direct electrical connection to the metal pillar. The metal pillars are attached directly to top metal vias without a bond pad of metal. The elimination of the bond pad layer reduces the mask count, processing, and cost of the device. In addition, the elimination of the bond pad results in reduced die area requirements for the metal pillar.

Wafer processing techniques, or methods for forming semiconductor rides, are disclosed for fabricating plated pillar dies having die-level electromagnetic interference (EMI) shield layers. In embodiments, the method includes depositing a metallic seed layer over a semiconductor wafer and contacting die pads thereon. An electroplating process is then performed to compile plated pillars on the metallic seed layer and across the semiconductor wafer. Following electroplating, selected regions of the metallic seed layer are removed to produce electrical isolation gaps around a first pillar type, while leaving intact portions of the metallic seed layer to yield a wafer-level EMI shield layer. The semiconductor wafer is separated into singulated plated pillar dies, each including a die-level EMI shield layer and plated pillars of the first pillar type electrically isolated from the EMI shield layer.

Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes an interconnect structure overlying a semiconductor substrate and comprising a conductive wire. A passivation structure overlies the interconnect structure. An upper conductive structure overlies the passivation structure and comprises a first conductive layer, a dielectric layer, and a second conductive layer. The first conductive layer is disposed between the dielectric layer and the passivation structure. The second conductive layer extends along a top surface of the dielectric layer and penetrates through the first conductive layer and the passivation structure to the conductive wire.

An integrated circuit chip includes an SOI substrate having a structure in which a bulk substrate, a buried insulating film, and a semiconductor body layer are sequentially stacked, a conductive ion implantation region formed at a position adjacent to the buried insulating film in the bulk substrate, an integrated circuit portion formed on an active surface of the semiconductor body layer, and a penetrating electrode portion arranged at a position spaced apart from the integrated circuit portion in a horizontal direction, the penetrating electrode portion penetrating the semiconductor body layer and the buried insulating layer in a vertical direction, and the penetrating electrode portion connected to the conductive ion implantation region. An integrated circuit package and a display device include the integrated circuit chip.

An integrated circuit chip includes an SOI substrate having a structure in which a bulk substrate, a buried insulating film, and a semiconductor body layer are sequentially stacked, a conductive ion implantation region formed at a position adjacent to the buried insulating film in the bulk substrate, an integrated circuit portion formed on an active surface of the semiconductor body layer, and a penetrating electrode portion arranged at a position spaced apart from the integrated circuit portion in a horizontal direction, the penetrating electrode portion penetrating the semiconductor body layer and the buried insulating layer in a vertical direction, and the penetrating electrode portion connected to the conductive ion implantation region. An integrated circuit package and a display device include the integrated circuit chip.

Various embodiments of the present disclosure are directed towards a semiconductor structure including a bond bump disposed on an upper surface of an upper conductive structure. The upper conductive structure overlies a substrate. A buffer layer is disposed along the upper surface of the upper conductive structure. The bond bump comprises a sidewall having a straight sidewall segment overlying a curved sidewall segment.

The present disclosure relates to the field of semiconductor technology, and discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a first solder layer, a barrier layer, and a second solder layer. The metal pad is disposed on the semiconductor substrate; the bump is arranged on the metal pad; the barrier layer is configured on the side of the bump away from the metal pad. The barrier layer includes a first surface and a second surface. The first solder layer is arranged between the bump and the first surface of the barrier layer. The second solder layer is configured on the second surface of the barrier layer. Since the first solder layer and the second solder layer are formed by reflowed and melt solder at a high temperature and can be stretched, the height of the second solder can be adjusted automatically, which reduces the non-wetting problem caused by the package substrate deformation after reflow.

A semiconductor structure includes a substrate, a MIM capacitor disposed over the substrate, a first insulating layer disposed over the MIM capacitor, an ONON stack disposed over the first insulating layer, a connecting via disposed in the first insulating layer, and a connecting pad disposed in the ONON stack and in contact with the connecting via. The ONON stack covers sidewalls of the connecting pad and a portion of a top surface of the connecting pad. The ONON stack includes a first silicon oxide layer, a first silicon nitride layer, a second silicon oxide layer and a second silicon nitride layer upwardly disposed over the first insulating layer. A thickness of the second silicon nitride layer is greater than a thickness of the second silicon oxide layer and greater than a thickness of the first silicon nitride layer.