A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a chemical cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.

A semiconductor device assembly that includes a first side of a semiconductor device supported on a substrate to permit the processing of a second side of the semiconductor device. A filler material deposited on the semiconductor device supports the semiconductor device on the substrate. The filler material does not adhere to the semiconductor device or the substrate. Alternatively, the filler material may be deposited on the substrate. Instead of a filler material, the substrate may include a topography configured to support the semiconductor device. Adhesive applied between an outer edge of the first side of the semiconductor and the substrate bonds the outer edge of the semiconductor device to the substrate to form a semiconductor device assembly. A second side of the semiconductor device may then be processed and the outer edge of the semiconductor device may be cut off to release the semiconductor device from the assembly.

Methods, apparatuses, and systems for substrate processing for lowering contact resistance in at least contact pads of a semiconductor device are provided herein. In some embodiments, a method of substrate processing for lowering contact resistance of contact pads includes: circulating a cooling fluid in at least one channel of a pedestal; and exposing a backside of the substrate located on the pedestal to a cooling gas to cool a substrate located on the pedestal to a temperature of less than 70 degrees Celsius. In some embodiments in accordance with the present principles, the method can further include distributing a hydrogen gas or hydrogen gas combination over the substrate.

Provided is a semiconductor device with higher reliability and longer life which can suppress an increase in production costs. A semiconductor device includes: a semiconductor element; a top electrode on an upper surface of the semiconductor element; and a conductive metal plate containing copper as a main component and solid-state diffusion bonded to the top electrode of the semiconductor element.

A method of manufacturing a display apparatus in which corrosion of an electrode due to a battery reaction does not occur, and corresponding apparatuses with excellent display characteristics are disclosed. In one example, the method includes forming a first electrode having a first conductive material and connected thereto a second electrode having a second conductive material respectively inside and outside a display area. First opening portions are formed on an interlayer insulation film that covers the electrodes such that a part of the first electrode is exposed. Second opening portions similarly leave a part of the second electrode exposed. An anisotropic conductive layer is formed on the exposed second electrode, and then the first opening portions, the second opening portions, and the interlayer insulation film are exposed to a liquid containing an electrolyte.

A method for direct bonding an electronic chip onto a substrate or another electronic chip, the method including: carrying out a hydrophilic treatment of a portion of, a surface of the electronic chip and of a portion of a surface of the substrate or of the other electronic chip; depositing an aqueous fluid on the portion of the surface of the substrate or of the second electronic chip; depositing the portion of the surface of the electronic chip on the aqueous fluid; drying the aqueous fluid until the portion of the surface of the electronic chip is rigidly connected to the portion of the surface of the substrate or of the other electronic chip: and during at least part of the drying of the aqueous fluid, emitting ultrasound into the aqueous fluid through the substrate or the other electronic chip.

A compound and method of use thereof consisting of an A-staged thermoplastic-polyimide (TPI) adhesive, a viscous uncured liquid of polyamic-acid polymer (PAA), the TPI precursor, synthesized and dissolved in a polar aprotic organic solvent, and including, as appropriate, combinations of flat particulate inorganic ceramic and/or metallic electrically insulating, and/or electrically conducting, and/or thermally conducting fillers for interface-bonding to create a robust joint between surfaces with conventional lamination processes that utilize relatively moderate temperatures and applied pressures, such particles resulting in the reduction of the occurrence and size of gas voids within the adhesive bondline.

A compound and method of use thereof consisting of an A-staged thermoplastic-polyimide (TPI) adhesive, a viscous uncured liquid of polyamic-acid polymer (PAA), the TPI precursor, synthesized and dissolved in a polar aprotic organic solvent, and including, as appropriate, combinations of flat particulate inorganic ceramic and/or metallic electrically insulating, and/or electrically conducting, and/or thermally conducting fillers for interface-bonding to create a robust joint between surfaces with conventional lamination processes that utilize relatively moderate temperatures and applied pressures, such particles resulting in the reduction of the occurrence and size of gas voids within the adhesive bondline.

The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

A microelectronic device includes a metal layer on a first dielectric layer. An etch stop layer is disposed over the metal layer and on the dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide, and is less than 10 nanometers thick. A second dielectric layer is disposed over the etch stop layer. The second dielectric layer is removed from an etched region which extends down to the etch stop layer. The etched region extends at least partially over the metal layer. In one version of the microelectronic device, the etch stop layer may extend over the metal layer in the etched region. In another version, the etch stop layer may be removed in the etched region. The microelectronic device is formed by etching the second dielectric layer using a plasma etch process, stopping on the etch stop layer.