Patent classifications
H01L2224/0381
SIDEWALL SPACER TO REDUCE BOND PAD NECKING AND/OR REDISTRIBUTION LAYER NECKING
In some embodiments, an integrated chip (IC) is provided. The IC includes a metallization structure disposed over a semiconductor substrate, where the metallization structure includes an interconnect structure disposed in an interlayer dielectric (ILD) structure. A passivation layer is disposed over the metallization structure, where an upper surface of the interconnect structure is at least partially disposed between opposite inner sidewalls of the passivation layer. A sidewall spacer is disposed along the opposite inner sidewalls of the passivation layer, where the sidewall spacer has rounded sidewalls. A conductive structure is disposed on the passivation layer, the rounded sidewalls of the sidewall spacer, and the upper surface of the interconnect structure.
METHODS AND APPARATUS FOR PROCESSING A SUBSTRATE
Methods and apparatus for processing a substrate are provided herein. For example, a method for processing a substrate can includes selectively etching from a substrate disposed in the PVD chamber an exposed first layer of material, covering an underlying second layer of material, and adjacent to an exposed third layer of material, using both process gas ions and metal ions formed from a target of the PVD chamber, in an amount sufficient to expose the second layer of material while simultaneously depositing a layer of metal onto the third layer of material; and subsequently depositing metal from the target onto the second layer of material.
METHODS AND APPARATUS FOR PROCESSING A SUBSTRATE
Methods and apparatus for processing a substrate are provided herein. For example, a method for processing a substrate can includes selectively etching from a substrate disposed in the PVD chamber an exposed first layer of material, covering an underlying second layer of material, and adjacent to an exposed third layer of material, using both process gas ions and metal ions formed from a target of the PVD chamber, in an amount sufficient to expose the second layer of material while simultaneously depositing a layer of metal onto the third layer of material; and subsequently depositing metal from the target onto the second layer of material.
Semiconductor device including a reactant metal layer disposed between an aluminum alloy film and a catalyst metal film and method for manufacturing thereof
A technology capable of reducing contamination of a semiconductor substrate above which a nickel film is disposed is provided. A semiconductor device includes: a semiconductor substrate; an aluminum alloy film disposed on at least one of a front surface and a back surface of the semiconductor substrate; a catalyst metal film disposed above the aluminum alloy film and exhibiting catalytic activity for autocatalytic reaction that deposits nickel; an electroless nickel plating film disposed on the catalyst metal film; and a reactant layer disposed between the aluminum alloy film and the catalyst metal film and containing metal of the catalyst metal film.
Redistribution layer metallic structure and method
The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device of an embodiment includes: a semiconductor substrate; a first insulating layer provided on or above the semiconductor substrate; an aluminum layer provided on the first insulating layer; a second insulating layer provided on the first insulating layer, the second insulating layer covering a first region of a surface of the aluminum layer; and an aluminum oxide film provided on a second region other than the first region of the surface of the aluminum layer, the aluminum oxide film including -alumina as a main component, and a film thickness of the aluminum oxide film being equal to or larger than 0.5 nm and equal to or smaller than 3 nm.
Shutter Disk
Describes are shutter disks comprising one or more of titanium (Ti), barium (Ba), or cerium (Ce) for physical vapor deposition (PVD) that allows pasting to minimize outgassing and control defects during etching of a substrate. The shutter disks incorporate getter materials that are highly selective to reactive gas molecules, including O.sub.2, CO, CO.sub.2, and water.
Shutter Disk
Describes are shutter disks comprising one or more of titanium (Ti), barium (Ba), or cerium (Ce) for physical vapor deposition (PVD) that allows pasting to minimize outgassing and control defects during etching of a substrate. The shutter disks incorporate getter materials that are highly selective to reactive gas molecules, including O.sub.2, CO, CO.sub.2, and water.
Treatment, before the bonding of a mixed Cu-oxide surface, by a plasma containing nitrogen and hydrogen
A method for bonding a first surface provided with at least one copper area surrounded by a silicon oxide area to a second surface includes an operation of treatment of the first surface by a plasma, before placing the first surface in contact with the second surface. The plasma is formed from a gas source containing a silicon oxide nitriding agent and a copper oxide reducing agent containing hydrogen. The gas source may include an N.sub.2 and NH.sub.3 and/or H.sub.2 gas mixture or a N.sub.2O and H.sub.2 gas mixture, or ammonia, which is then used both as a nitriding agent and as a reducing agent. The plasma obtained from this gas source then necessarily contains nitrogen and hydrogen, which enables, in a single operation, to provide a high-performance bonding between the first and second surfaces.
Bonding process with inhibited oxide formation
First and second contacts are formed on first and second wafers from disparate first and second conductive materials, at least one of which is subject to surface oxidation when exposed to air. A layer of oxide-inhibiting material is disposed over a bonding surface of the first contact and the first and second wafers are positioned relative to one another such that a bonding surface of the second contact is in physical contact with the layer of oxide-inhibiting material. Thereafter, the first and second contacts and the layer of oxide-inhibiting material are heated to a temperature that renders the first and second contacts and the layer of oxide-inhibiting material to liquid phases such that at least the first and second contacts alloy into a eutectic bond.