A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads includes a metal bond pad area. A cobalt including connection layer is deposited directly on the metal bond pad area. The cobalt including connection layer is patterned to provide a cobalt bond pad surface for the plurality of bond pads, and a solder material is formed on the cobalt bond pad surface.

A method for manufacturing an electronic component includes positioning a first surface of a first component facing a second surface of a second component in a first state. The first surface has a first pad having a first center. The second surface has a second pad having a second center. At least one of the first or second pads includes a metal member. The method includes melting the metal member and moving the first and second components until the melted metal member contacts both pads, moving at least one of the first or second components in a direction along the first surface, and solidifying the metal member in a second state. A first distance in a direction along the first surface between the first and second centers in the first state is longer than a second distance in the direction between the first and second centers in the second state.

Flux formulations and solder attachment during the fabrication of electronic device assemblies are described. One flux formation includes a flux component and a metal particle component, the metal particle component being present in an amount of from 5 to 35 volume percent of the flux formulation. In one feature of certain embodiments, the metal particle component includes solder particles. Other embodiments are described and claimed.

Flux formulations and solder attachment during the fabrication of electronic device assemblies are described. One flux formation includes a flux component and a metal particle component, the metal particle component being present in an amount of from 5 to 35 volume percent of the flux formulation. In one feature of certain embodiments, the metal particle component includes solder particles. Other embodiments are described and claimed.

The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.

A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.

Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector.

The present disclosure relates to a semiconductor package having a substrate structure with selective surface finishes, and a process for making the same. The disclosed semiconductor package includes a substrate body, a first metal structure having a first finish area and a second finish area, a second metal structure having a third finish area, a surface finish, and a tuning wire. The first metal structure and the second metal structure are formed over the substrate body. The surface finish is provided over the first finish area of the first metal structure and at least a portion of the third finish area of the second metal structure. The surface finish is not provided over the second finish area of the first metal structure. The tuning wire is coupled between the first finish area and at least one portion of the third finish area.

Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.

Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.