Patent classifications
H01L2224/0383
Methods of Forming Connector Pad Structures, Interconnect Structures, and Structures Thereof
Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.
Methods of Forming Connector Pad Structures, Interconnect Structures, and Structures Thereof
Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.
Image sensor packages and methods of fabricating the same
An image sensor package includes a die having an active side surface and a backside surface opposite to each other and having a bonding pad disposed on the active side surface, a through via penetrating the die and being electrically connected to the bonding pad, and a first dielectric layer disposed between the through via and the die. The first dielectric layer extends to cover the backside surface of the die. A redistribution line is disposed on the first dielectric layer and is electrically connected to the through via. The redistribution line extends onto the first dielectric layer on the backside surface of the die. A second dielectric layer is disposed on the first dielectric layer to cover the redistribution line and to extend onto an outer sidewall of the die. Related methods are also provided.
Image sensor packages and methods of fabricating the same
An image sensor package includes a die having an active side surface and a backside surface opposite to each other and having a bonding pad disposed on the active side surface, a through via penetrating the die and being electrically connected to the bonding pad, and a first dielectric layer disposed between the through via and the die. The first dielectric layer extends to cover the backside surface of the die. A redistribution line is disposed on the first dielectric layer and is electrically connected to the through via. The redistribution line extends onto the first dielectric layer on the backside surface of the die. A second dielectric layer is disposed on the first dielectric layer to cover the redistribution line and to extend onto an outer sidewall of the die. Related methods are also provided.
Methods of forming connector pad structures, interconnect structures, and structures thereof
Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.
Methods of forming connector pad structures, interconnect structures, and structures thereof
Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.
Methods of Forming Connector Pad Structures, Interconnect Structures, and Structures Thereof
Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.
Methods of Forming Connector Pad Structures, Interconnect Structures, and Structures Thereof
Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.
INTEGRATED CIRCUIT (IC) STRUCTURES WITH THERMAL PATH TO CARRIER SUBSTRATE
A semiconductor structure includes a device layer having a transistor device and a PN junction structure coupled to the transistor device. The PN junction structure includes a first doped region and a second doped region, and the first doped region is electrically connected to a gate stack of the transistor device. The semiconductor structure includes a frontside interconnect structure over a frontside of the device layer, the frontside interconnect structure includes thermal path metal features electrically connected to the second doped region of the PN junction structure. The semiconductor structure includes a bonding oxide layer over the frontside interconnect structure, the bonding oxide layer embeds a thermal path metal contact electrically connected to the thermal path metal features. The semiconductor structure includes a carrier substrate over the bonding oxide layer, the carrier substrate landing on a top surface of the thermal path metal contact.
DIELECTRIC WINDOWS FOR GROUPS OF VIAS THROUGH SEMICONDUCTOR SUBSTRATES
Methods, systems, and devices for dielectric windows for groups of vias through semiconductor substrates are described. For example, a semiconductor component (e.g., a semiconductor die, a semiconductor wafer) may be formed with one or more dielectric windows through a substrate of the semiconductor component, through which a group of multiple vias may be formed to support signaling with circuitry of the semiconductor component. In some implementations, a set of multiple cavities may be formed through a given dielectric portion and, in each of the multiple cavities, a conductive portion (e.g., one or more conductive materials) may be formed to support multiple electrically isolated contacts. In various examples, such vias may include contacts themselves (e.g., for vias that extend to the surface of the semiconductor component), or may be otherwise coupled with (e.g., contiguous with, electrically coupled with) a contact portion that has a different cross-section than the vias.