The present disclosure relates to semiconductor structures and, more particularly, to wafer bond interconnect structures and methods of manufacture. The structure includes: a plurality of sub-pixels each comprising a contact plate; and redundant connections at opposite corners of each sub-pixel on a backside of the contact plate.

The present disclosure relates to semiconductor structures and, more particularly, to wafer bond interconnect structures and methods of manufacture. The structure includes: a plurality of sub-pixels each comprising a contact plate; and redundant connections at opposite corners of each sub-pixel on a backside of the contact plate.

A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor device comprising forming interconnection structures by at least part performing a lateral plating process, and a semiconductor device manufactured thereby.

A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor device comprising forming interconnection structures by at least part performing a lateral plating process, and a semiconductor device manufactured thereby.

A method for bonding chips to a landing wafer is disclosed. In one aspect, a volume of alignment liquid is dispensed on a wettable surface of the chip so as to become attached to the surface, after which the chip is moved towards the bonding site on the wafer, the bonding site equally being provided with a wettable surface. A liquid bridge is formed between the chip and the bonding site on the substrate wafer, enabling self-alignment of the chip. Dispensing alignment liquid on the chip and not the wafer is advantageous in terms of mitigating unwanted evaporation of the liquid prior to bonding.

A method for assembling a packaged integrated circuit for operating reliably at elevated temperatures is provided. The method includes providing an extended bond pad over an original die pad of an extracted die to create a modified extracted die. The extracted die is a fully functional semiconductor die that has been removed from a finished packaged integrated circuit. The method also includes placing the modified extracted die into a cavity of a package base and bonding a new bond wire between the extended bond pad and a lead of the package base or a downbond, and sealing a package lid to the package base and the cavity of the package.

A method for assembling a packaged integrated circuit for operating reliably at elevated temperatures is provided. The method includes providing an extended bond pad over an original die pad of an extracted die to create a modified extracted die. The extracted die is a fully functional semiconductor die that has been removed from a finished packaged integrated circuit. The method also includes placing the modified extracted die into a cavity of a package base and bonding a new bond wire between the extended bond pad and a lead of the package base or a downbond, and sealing a package lid to the package base and the cavity of the package.

Interconnects and methods of fabricating a plurality of interconnects. The method includes depositing a conformal layer of a plating base in each of a plurality of vias, and depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias. The method also includes depositing a plating metal over the plating base in each of the plurality of vias, the depositing resulting in each of the plurality of vias being completely filled or incompletely filled, performing a chemical mechanical planarization (CMP), and performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal. A second iteration of the depositing the plating metal over the plating base is performed in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled.

A solder connection may be surrounded by a solder locking layer (1210, 2210) and may be recessed in a hole (1230) in that layer. The recess may be obtained by evaporating a vaporizable portion (1250) of the solder connection. Other features are also provided.

A solder connection may be surrounded by a solder locking layer (1210, 2210) and may be recessed in a hole (1230) in that layer. The recess may be obtained by evaporating a vaporizable portion (1250) of the solder connection. Other features are also provided.