H01L2224/03912

Mechanisms for forming post-passivation interconnect structure

Mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.

Method of forming vias using silicon on insulator substrate

Apparatuses and methods using a silicon on insulator (SOI) substrate are described. An example apparatus includes: a substrate including a first surface and a second surface opposite to the first surface; a circuit formed in the first surface; a first electrode through the substrate from the first surface to the second surface; and a first insulative film around the first electrode. The first electrode includes: a first portion formed in the substrate; and a second portion continuous to the first portion and protruding from the second surface. The first insulative film is formed between the first portion of the first electrode in the substrate and extending to a side surface of the second portion of the first electrode.

Etching agent for copper or copper alloy
09790600 · 2017-10-17 · ·

Object is to provide an etching solution which generates less foam and can etch copper or copper alloy at high selectivity when used in a step of etching copper or 5 copper alloy in an electronic substrate having both of copper or copper alloy and nickel. The etching solution to be used in a step of selectively etching copper or copper alloy in an electronic substrate having both of copper or copper alloy and nickel has, as essential components thereof, (A) a linear alkanolamine, (B) a chelating agent having an acid group in the molecule thereof, and (C) hydrogen peroxide.

Package structure and manufacturing method

A package structure and a manufacturing method are provided. The package structure includes a semiconductor substrate and a first conductive feature over the semiconductor substrate. The package structure also includes a substrate and a second conductive feature over the substrate. The second conductive feature is bonded with the first conductive feature through a bonding structure. The package structure further includes a protection material surrounding the bonding structure, and the protection material is in direct contact with a side surface of the first conductive feature.

ELECTRONIC PART, ELECTRONIC DEVICE, AND ELECTRONIC APPARATUS
20170250153 · 2017-08-31 · ·

An electronic part includes a substrate, an insulating film formed over the substrate, a first pillar electrode, a first solder formed over the first pillar electrode, a second pillar electrode, and a second solder formed over the second pillar electrode. The first pillar electrode over which the first solder is formed is formed over a first region of an insulating film including a level difference between a first opening portion and a peripheral portion of the first opening portion. The second pillar electrode over which the second solder is formed is formed over a second region of the insulating film including a second opening portion whose opening area is larger than that of the first opening portion. For example, the second pillar electrode over which the second solder is formed is formed over the second opening portion of the insulating film.

Substrate bonding structure and substrate bonding method

A device (2) is formed on a main surface of a substrate (1). The main surface of the substrate (1) is bonded to the undersurface of the counter substrate (14) via the bonding member (11,12,13) in a hollow state. A circuit (17) and a bump structure (26) are formed on the top surface of the counter substrate (14). The bump structure (26) is positioned in a region corresponding to at least the bonding member (11,12,13), and has a higher height than that of the circuit (17).

FINGERPRINT SENSOR AND MANUFACTURING METHOD THEREOF
20170243798 · 2017-08-24 ·

A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise a sensing area on a bottom side of a die without top side electrodes that senses fingerprints from the top side, and/or that comprise a sensor die directly electrically connected to conductive elements of a plate through which fingerprints are sensed.

Bump structures, semiconductor device and semiconductor device package having the same

The present disclosure relates to bump structures and a semiconductor device and semiconductor device package having the same. The semiconductor device includes a body, at least one conductive metal pad and at least one metal pillar. The body includes a first surface. The at least one conductive metal pad is disposed on the first surface. Each metal pillar is formed on a corresponding conductive metal pad. Each metal pillar has a concave side wall and a convex side wall opposite the first concave side wall, and the concave side wall and the convex side wall are orthogonal to the corresponding conductive metal pad.

Bump structures, semiconductor device and semiconductor device package having the same

The present disclosure relates to bump structures and a semiconductor device and semiconductor device package having the same. The semiconductor device includes a body, at least one conductive metal pad and at least one metal pillar. The body includes a first surface. The at least one conductive metal pad is disposed on the first surface. Each metal pillar is formed on a corresponding conductive metal pad. Each metal pillar has a concave side wall and a convex side wall opposite the first concave side wall, and the concave side wall and the convex side wall are orthogonal to the corresponding conductive metal pad.

Leadframes in Semiconductor Devices
20220037277 · 2022-02-03 ·

In one instance, a method of forming a semiconductor package with a leadframe includes cutting, such as with a laser, a first side of a metal strip to a depth D1 according to a cutting pattern to form a first plurality of openings, which may be curvilinear. The method further includes etching the second side of the metal strip to a depth D2 according to a photoresist pattern to form a second plurality of openings. At least some of the first plurality of openings are in fluid communication with at least some of the second plurality of openings to form a plurality of leadframe leads. The depth D1 is shallower than a height H of the metal strip, and the depth D2 is also shallower than the height H. Other embodiments are presented.