Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.

Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.

The present invention: makes it possible to improve the reliability of a semiconductor device; and provides a method of manufacturing the semiconductor device comprising the steps of (a) providing a semiconductor wafer having a pad electrode, a first conductive layer comprised of copper, a photoresist film, and a second conductive layer comprised of gold, (b) forming a protective film comprised of iodine on the surface of the second conductive layer, (c) removing the photoresist film, (d) irradiating the protective film with argon ions and removing the protective film, and (e) bringing a part of a bonding wire into contact with the surface of the second conductive layer.

During the manufacture of a semiconductor package, a semiconductor wafer including a plurality of bond pads on a surface of the wafer is provided and the surface of the wafer is covered with a dielectric material to form a dielectric layer over the bond pads. Portions of the dielectric layer corresponding to positions of the bond pads are removed to form a plurality of wells, wherein each well is configured to form a through-hole between top and bottom surfaces of the dielectric layer for exposing each bond pad. A conductive material is then deposited into the wells to form a conductive layer between the bond pads and a top surface of the dielectric layer. Thereafter, the semiconductor wafer is singulated to form a plurality of semiconductor packages.

According to one embodiment, a semiconductor device includes a first semiconductor substrate having a first wiring electrode on a first surface thereof, a first protective layer on the semiconductor substrate, having an opening therethrough at the location of first wiring electrode, a first bump electrode in the opening of the first protective layer, the first bump electrode including a base overlying the wiring electrode and an opposed bump receiving surface, and a first bump comprising a bump diameter of 30 m or less connected to the first bump electrode. The width of the base of the first bump electrode within the opening is equal to or less than 1.5 times the thickness of the first protective layer.

An inventive semiconductor device includes: a semiconductor chip including an integrated circuit; a plurality of electrode pads provided on the semiconductor chip and connected to the integrated circuit; a rewiring to which the electrode pads are electrically connected together, the rewiring being exposed on an outermost surface of the semiconductor chip and having an exposed surface area greater than the total area of the electrode pads; and a resin package which seals the semiconductor chip.

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.

Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (first wires) extend from a surface of the substrate. Second wire bond wires (second wires) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.

The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A conductive structure is disposed on the conductive pad, and a passive device is also disposed on the conductive pad, wherein the passive device has a first portion located above the second passivation layer and a second portion passing through the second passivation layer. A solderability preservative film covers the first portion of the passive device, and an under bump metallurgy (UBM) layer covers the second portion of the passive device and a portion of the conductive structure.

To provide a semiconductor device having improved reliability. A method of manufacturing the semiconductor device includes connecting a wire comprised of copper with a conductive layer formed on the pad electrode of a semiconductor chip, heat treating the semiconductor chip, and then sealing the semiconductor chip and the wire with a resin.