Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad.

An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad.

Representative implementations of devices and techniques provide a temporary access point (e.g., for testing, programming, etc.) for a targeted interconnect located among multiple finely spaced interconnects on a surface of a microelectronic component. One or more sacrificial layers are disposed on the surface of the microelectronic component, overlaying the multiple interconnects. An insulating layer is disposed between a conductive layer and the surface, and includes a conductive via through the insulating layer that electrically couples the conductive layer to the target interconnect. The sacrificial layers are configured to be removed after the target interconnect has been accessed, without damaging the surface of the microelectronic component.

A method of packaging a semiconductor device having a bond pad on a surface thereof includes forming a redistribution material electrically coupled to the bond pad, forming a dielectric material over the redistribution material, and removing a first portion of the dielectric material to expose a first portion of the redistribution material. Semiconductor packages may include a redistribution layer having a first portion adjacent and coupled to a first contact of the package, a second portion exposed by a first opening in a dielectric material, and a redistribution line electrically coupled to a first bond pad, the first portion, and the second portion. Such a package may be tested placing at least one probe needle in contact with at least one terminal of the package, providing a test signal from the probe needle to the package through the terminal, and detecting signals using the needle.

In a wafer inspection step for testing electrical characteristics of an integrated circuit in a chip region (CP) formed in a wafer, a first probe needle having a relatively small diameter is brought into contact with a first pad for small current and a second probe needle having a relatively large diameter is brought into contact with a second pad for large current. A wiring and a field effect transistor, which are used for forming the integrated circuit, are arranged directly under the first pad to which a relatively small needle pressure of the first probe needle is to be applied. On the other hand, a wiring and a field effect transistor, which are used for forming the integrated circuit, are not arranged directly under the second pad to which a relatively large needle pressure of the second probe needle is to be applied.

A semiconductor package includes a substrate, a semiconductor layer on the substrate, a wiring structure on the semiconductor layer, a connection pad on and connected to the wiring structure, a test pad on and connected to the wiring structure, the test and connection pads being horizontally spaced from each other, a first liner film on the wiring structure and having a first bonding pad trench, a second liner film on the first liner film and having a second bonding pad trench, a first bonding pad including a barrier layer in contact with the first liner film and a metal layer on the barrier layer, and a second bonding pad filling an inner portion of the second bonding pad trench and in contact with the second liner film, wherein the second liner film integrally covers upper surfaces of the barrier layer and metal layer.

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed over the substrate. The semiconductor device structure also includes a protection layer formed over the conductive pad, and the protection layer has a trench. The semiconductor device structure further includes a conductive structure accessibly arranged through the trench of the protection layer and electrically connected to the conductive pad. The conductive structure has a curved top surface that defines an apex, and an apex of the curved top surface is higher than a top surface of the protection layer.

A method for use in manufacturing semiconductor devices such as, e.g., semiconductor power devices includes providing: a semiconductor die provided with bonding pads, a lead frame for the semiconductor die, a wire bonding layout including electrically conductive wires coupling bonding pads of the semiconductor die with leads in the lead frame. One or more bonding pads of the semiconductor die is/are coupled to a respective lead in the lead frame via a plurality of wires with a plurality of mutually insulated testing lands in the respective lead, so that the plurality of wires are coupled to respective testing lands. The electrical connection between such a bonding pad and the respective lead may be tested by testing the individual electrical connections between the bonding pad and the plurality of testing lands.

A semiconductor integrated circuit device capable of stably forming a fuse element that is used to adjust the characteristics of the semiconductor integrated circuit device, and a method of manufacturing the semiconductor integrated circuit device are provided. The thickness of an interlayer insulating film above the fuse element is reduced by using an amorphous silicon layer that is formed by sputtering as a material of the fuse element, and by forming the amorphous silicon layer at the same time as metal wiring is formed. The steady ease of laser trimming processing is thus accomplished in the semiconductor integrated circuit device and the method of manufacturing the semiconductor integrated circuit device.