A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a first surface, a second surface opposing the first surface, and sidewalls defining a recess that passes through the semiconductor substrate. A first interconnect layer is within a first dielectric structure disposed along the second surface, and a bonding pad is in the recess and extends to the first interconnect layer. A dielectric filling layer is also within the recess. The dielectric filling layer has an opening over a portion of the bonding pad and a curved upper surface over the bonding pad. A nickel layer is over the bonding pad and in the opening.

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Provided is a semiconductor device including: a first substrate having a first primary surface, a second primary surface, and a side surface; a semiconductor element formed on the first primary surface; a first electrode formed on the first primary surface and connected to the semiconductor element on the first primary surface; a second electrode formed on the second primary surface; a through-electrode formed so as to penetrate the first substrate and connecting the first electrode and the second electrode to each other; a second substrate bonded to the first substrate so as to face the first primary surface; and a third electrode formed on the side surface of the first substrate and connected to the second electrode.

A semiconductor device includes a semiconductor die. The semiconductor die includes a device layer, an interconnect layer over the device layer, a conductive pad over the interconnect layer, a conductive seed layer directly on the conductive pad, and a passivation layer encapsulating the conductive pad and the conductive seed layer. The conductive pad is between the interconnect layer and the conductive seed layer.

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed over the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad, and the protection layer has a trench. The semiconductor device structure includes a conductive structure formed in the trench and on the protection layer. The conductive structure is electrically connected to the conductive pad, and the conductive structure has a concave top surface, and the lowest point of the concave top surface is higher than the top surface of the protection layer.

A semiconductor integrated circuit device capable of stably forming a fuse element that is used to adjust the characteristics of the semiconductor integrated circuit device, and a method of manufacturing the semiconductor integrated circuit device are provided. The thickness of an interlayer insulating film above the fuse element is reduced by using an amorphous silicon layer that is formed by sputtering as a material of the fuse element, and by forming the amorphous silicon layer at the same time as metal wiring is formed. The steady ease of laser trimming processing is thus accomplished in the semiconductor integrated circuit device and the method of manufacturing the semiconductor integrated circuit device.

To enhance reliability of a test by suppressing defective bonding of a solder in the test of a semiconductor device, a method of manufacturing the semiconductor device includes: preparing a semiconductor wafer that includes a first pad electrode provided with a first cap film and a second pad electrode provided with a second cap film. Further, a polyimide layer that includes a first opening on the first pad electrode and a second opening on the second pad electrode is formed, and then, a rearrangement wiring that is connected to the second pad electrode via the second opening is formed. Next, an opening is formed in the polyimide layer such that an organic reaction layer remains on each of the first pad electrode and a bump land of the rearrangement wiring, then heat processing is performed on the semiconductor wafer, and then, a bump is formed on the rearrangement wiring.

A semiconductor device includes a semiconductor chip substrate with a chip region and a scribe lane region, center and boundary pads respectively provided on the chip and scribe lane regions, a lower insulating structure provided on the chip region and the scribe lane region, a first conductive pattern including a contact portion, a conductive line portion, and a bonding pad portion, and an upper insulating structure defining first and second openings formed on the bonding pad portion and the boundary pad. The lower insulating structure includes a plurality of lower insulating layers, which are sequentially stacked on the substrate, and each of which is a silicon-containing inorganic layer.

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor substrate having a first surface, a second surface, and a recess. The second surface is opposite to the first surface. The recess passes through the first semiconductor substrate. The semiconductor device structure includes a first wiring layer over the second surface. The semiconductor device structure includes a first bonding pad in the recess and extending to the first wiring layer so as to be electrically connected to the first wiring layer. The semiconductor device structure includes a nickel layer over the first bonding pad. The semiconductor device structure includes a gold layer over the nickel layer.