A semiconductor device includes a semiconductor die. The semiconductor die includes a device layer, an interconnect layer over the device layer, a conductive pad over the interconnect layer, a conductive seed layer directly on the conductive pad, and a passivation layer encapsulating the conductive pad and the conductive seed layer. The conductive pad is between the interconnect layer and the conductive seed layer.

A chip includes a core layer, at least one redistribution layer formed on the core layer, and at least one triple pad connected to a pad of the core layer through the at least one redistribution layer or at least one via connected to the at least one redistribution layer. The at least one triple pad includes a bonding pad, a redistribution layer pad connected to the at least one redistribution layer, and a test pad configured to perform a wafer level test. The bonding pad, the redistribution layer pad and the test pad are connected to one another through the at least one redistribution layer, and the test pad is disposed in a core area that overlaps the core layer.

A conductive terminal on an integrated circuit is provided. The conductive terminal includes a conductive pad, a dielectric layer, and a conductive via. The conductive pad is disposed on and electrically to the integrated circuit. The dielectric layer covers the integrated circuit and the conductive pad, the dielectric layer includes a plurality of contact openings arranged in array, and the conductive pad is partially exposed by the contact openings. The conductive via is disposed on the dielectric layer and electrically connected to the conductive pad through the contact openings. The conductive via includes a plurality of convex portions arranged in array. The convex portions are distributed on a top surface of the conductive via, and the convex portions are corresponding to the contact openings.

A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

To enhance reliability of a test by suppressing defective bonding of a solder in the test of a semiconductor device, a method of manufacturing the semiconductor device includes: preparing a semiconductor wafer that includes a first pad electrode provided with a first cap film and a second pad electrode provided with a second cap film. Further, a polyimide layer that includes a first opening on the first pad electrode and a second opening on the second pad electrode is formed, and then, a rearrangement wiring that is connected to the second pad electrode via the second opening is formed. Next, an opening is formed in the polyimide layer such that an organic reaction layer remains on each of the first pad electrode and a bump land of the rearrangement wiring, then heat processing is performed on the semiconductor wafer, and then, a bump is formed on the rearrangement wiring.

A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal trace under at least a first dielectric layer and a second dielectric layer. The metal trace is connected to a ball connection by a first via in the first dielectric layer and second via in the second dielectric layer. The metal trace is connected to a test pad at a connection point, where the connection point is under the first dielectric layer. The metal trace under at least the first dielectric layer and the second dielectric layer has increased stability and decreased susceptibility to cracking in least one of the ball connection, the connection point, the first via or the second via as compared to a metal trace that is not under at least a first dielectric layer and a second dielectric layer.

A semiconductor apparatus includes elements formed on a substrate, a first insulation layer, a first pad and a second pad arranged on the first insulation layer and located above the elements, and a second insulation layer that is arranged on the side surfaces and upper surfaces of the first pad and the second pad. The second insulation layer includes openings at upper surfaces of the first pad and the second pad. The thickness of the first pad and the second pad is 2 m or more, the thickness of the second insulation layer is less than or equal to of the thickness of the first pad and the second pad, and the distance between the first pad and the second pad is greater than or equal to four times the thickness of the first pad and the second pad.

A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal trace under at least a first dielectric layer and a second dielectric layer. The metal trace is connected to a ball connection by a first via in the first dielectric layer and second via in the second dielectric layer. The metal trace is connected to a test pad at a connection point, where the connection point is under the first dielectric layer. The metal trace under at least the first dielectric layer and the second dielectric layer has increased stability and decreased susceptibility to cracking in least one of the ball connection, the connection point, the first via or the second via as compared to a metal trace that is not under at least a first dielectric layer and a second dielectric layer.

A semiconductor device has a semiconductor wafer and a first conductive layer formed over the semiconductor wafer as contact pads. A first insulating layer formed over the first conductive layer. A second conductive layer including an interconnect site is formed over the first conductive layer and first insulating layer. The second conductive layer is formed as a redistribution layer. A second insulating layer is formed over the second conductive layer. An opening is formed in the second insulating layer over the interconnect site. The opening extends to the first insulating layer in an area adjacent to the interconnect site. Alternatively, the opening extends partially through the second insulating layer in an area adjacent to the interconnect site. An interconnect structure is formed within the opening over the interconnect site and over a side surface of the second conductive layer. The semiconductor wafer is singulated into individual semiconductor die.

A semiconductor chip and/or a semiconductor package including the same are disclosed. The semiconductor chip may include an integrated circuit on a substrate, a center pad electrically connected to the integrated circuit, a lower insulating structure on the center pad and having a contact hole exposing the center pad, the lower insulating structure including a plurality of lower insulating layers sequentially stacked on the substrate, a conductive pattern including a contact portion, a pad portion, a conductive line portion, the contact portion filling the contact hole, the pad portion including a test region and a bonding region, a conductive line portion on the lower insulating structure and connecting the contact portion to the pad portion, and an upper insulating structure on the conductive pattern and having a first opening exposing the pad portion, and the upper insulating structure including an upper insulating layer and a polymer layer.