In some embodiments, the present disclosure provides a conductive pads forming method. The conductive pads forming method may include providing a contact pad or a test pad electrically connected to a semiconductor component; and forming the conductive pads electrically connected to the contact pad or the test pad through the conductive routes, respectively.

Provided is a die stack structure including a first die and a second die. The first die and the second die are bonded together through a hybrid bonding structure. At least one of a first test pad of the first die or a second test pad of the second die has a protrusion of the at least one of the first test pad or the second test pad, and a bonding insulating layer of the hybrid bonding structure covers and contacts with the protrusion, so that the first test pad and the second test pad are electrically isolated from each other.

A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.

A semiconductor chip includes a chip body including a signal input/output circuit, a chip pad structure disposed on a surface of the chip body, the chip pad structure including first and second chip pads, the two chip pads having different surface areas, and a chip pad selection circuit disposed in the chip body and electrically connected to the signal input/output circuit and the chip pad structure. The chip pad selection circuit is configured to selectively and electrically connect one of the first and second chip pads to the signal input/output circuit.

A method of fabricating a semiconductor package includes forming a capping pattern on a chip pad of a semiconductor device. The semiconductor device includes a passivation pattern that exposes a portion of the chip pad, and the capping pattern covers the chip pad. The method further includes forming a redistribution layer on the capping pattern. Forming the redistribution layer includes forming a first insulation pattern on the capping pattern and the passivation pattern, forming a first opening in the first insulation pattern by performing exposure and development processes on the first insulation pattern, in which the first opening exposes a portion of the capping pattern, and forming a redistribution pattern in the first opening.

A method of manufacturing a die stack structure includes the following steps. A first bonding structure is formed over a front side of a first die. The method of forming the first bonding structure includes the following steps. A first bonding dielectric material is formed on a first test pad of the first die. A first blocking layer is formed over the first bonding dielectric material. A second bonding dielectric material and a first dummy metal layer are formed over the first blocking layer. The first dummy metal layer and the first test pad are electrically isolated from each other by the first blocking layer. Thereafter, a second bonding structure is formed over a front side of a second die. The first die and the second die are bonded through the first bonding structure and the second bonding structure.

Provided is a semiconductor structure including an interconnect structure, disposed over a substrate; a pad structure, disposed over and electrically connected to the interconnect structure, wherein the pad structure comprises a metal pad and a dielectric cap on the metal pad, and the pad structure has a probe mark recessed from a top surface of the dielectric cap into a top surface of the metal pad; a protective layer, conformally covering the top surface of the dielectric cap and the probe mark; and a bonding structure, disposed over the protective layer, wherein the bonding structure comprises: a bonding dielectric layer at least comprising a first bonding dielectric material and a second bonding dielectric material on the first bonding dielectric material; and a first bonding metal layer disposed in the bonding dielectric layer and penetrating through the protective layer and the dielectric cap to contact the metal pad.

Provided is a die stack structure including a first die and a second die. The first die and the second die are bonded together through a hybrid bonding structure. A bonding insulating layer of the hybrid bonding structure extends to contact with one interconnect structure of the first die or the second die.

Provided is a semiconductor structure including a pad disposed over and electrically connected to an interconnect structure, wherein the pad has a probe mark, and the probe mark has a concave surface; a protective layer conformally covering the pad and the probe mark; and a bonding structure disposed over the protective layer, wherein the bonding structure includes: a bonding dielectric layer includes a first bonding dielectric material and a second bonding dielectric material on the first bonding dielectric material; a first bonding metal layer including a via plug and a metal feature, wherein the via plug penetrates through the first bonding dielectric material and the protective layer to electrically connect to the pad having the probe mark, the metal feature is located on the via plug and the first bonding dielectric material, and the metal feature is laterally surrounded by the second bonding dielectric material.