An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.

The embodiments of the present invention discloses an arrangement of bond pads on an integrated circuit chip. The integrated circuit chip includes: a first row of bond pads; and a second row of bond pads, wherein bond pads in the first row are positioned alternately with bond pads in the second row, and a short side of the bond pads in the first row and the second row is parallel to a long side of the integrated circuit chip. With this arrangement of bond pads on the integrated circuit chip, the bond pads may occupy a reduced area of a surface of the integrated circuit chip.

A pad is formed on an interlayer insulating film, art insulating film is formed on the interlayer insulating film to cover the pad, and an opening portion exposing a part of the pad is formed in the insulating film. A metal film electrically connected to the pad is formed on the pad exposed from the opening portion and on the insulating film. The metal film integrally includes a first portion on the pad exposed from the opening portion and a second portion on the insulating film. An upper surface of the metal film has a wire bonding region for bonding a wire to the metal film and a probe contact region for bringing the probe into contact with the metal film, the wire bonding region is located on the first portion of the metal film, and the probe contact region is located on the second portion of the metal film.

Provided is a semiconductor structure including an interconnect structure, disposed over a substrate; a pad structure, disposed over and electrically connected to the interconnect structure, wherein the pad structure comprises a metal pad and a dielectric cap on the metal pad, and the pad structure has a probe mark recessed from a top surface of the dielectric cap into a top surface of the metal pad; a protective layer, conformally covering the top surface of the dielectric cap and the probe mark; and a bonding structure, disposed over the protective layer, wherein the bonding structure comprises: a bonding dielectric layer at least comprising a first bonding dielectric material and a second bonding dielectric material on the first bonding dielectric material; and a first bonding metal layer disposed in the bonding dielectric layer and penetrating through the protective layer and the dielectric cap to contact the metal pad.

A semiconductor substrate has a bond pad. The bond pad includes a layer of an aluminum alloy having a chemical composition including at least 0.3% by weight of at least one of Zn, Mg, Sc, Zr, Ti, Ag and/or Mn, with the balance being at least Al and incidental impurities.

Disclosed herein is a method that includes forming a contact plug to be embedded in a first insulating film formed on a semiconductor substrate; forming a probe pad on the first insulating film to contact with the contact plug; performing a test operation by probing the probe pad; removing the probe pad; forming a second insulating film to cover the contact plug after removing the probe pad; and forming a pad electrode to be embedded in the second insulating film.

A method includes forming a first passivation layer, forming a metal pad over the first passivation layer, forming a planarization layer having a planar top surface over the metal pad, and patterning the planarization layer to form a first opening. A top surface of the metal pad is revealed through the first opening. The method further includes forming a polymer layer extending into the first opening, and patterning the polymer layer to form a second opening. The top surface of the metal pad is revealed through the second opening.

In a method of manufacturing a semiconductor device according to one embodiment, after a semiconductor wafer including a non-volatile memory, a bonding pad and an insulating film comprised of an organic material is provided, a probe needle is contacted to a surface of the bonding pad located in a second region, and a data is written to the non-volatile memory. Here, the insulating film is formed by performing a first heat treatment to the organic material. Also, after a second heat treatment is performed to the semiconductor wafer, and the non-volatile memory to which the data is written is checked, a barrier layer and a first solder material are formed on the surface of the bonding pad located in a first region by using an electroplating method. Further, a bump electrode is formed in the first region by performing a third heat treatment to the first solder material.

A semiconductor device structure is provided, in some embodiments. The semiconductor device structure includes a semiconductor substrate having a first surface, a second surface, and sidewalls defining a recess that passes through the semiconductor substrate. The semiconductor device structure further includes an interconnect structure having one or more interconnect layers within a first dielectric structure that is disposed along the second surface. A conductive bonding structure is disposed within the recess and includes nickel. The conductive bonding structure has opposing outermost sidewalls that contact sidewalls of the interconnect structure.

According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.