A method to fabricate a modular die daisy chain design for wafer level chip scale package (WLCSP) board level reliability testing is described. A wafer is provided having pairs of solder balls electrically connected to each other by underlying metal pads. The wafer is singulated into dies of any of a plurality of sizes as required for testing. Thereafter one of the singulated dies is mounted to a test printed circuit board (PCB). The pairs of solder balls are electrically connected in a daisy chain on the test PCB.

Provided is a three-dimensional integrated circuit (3DIC) structure including a first die and a second die bonded together by a hybrid bonding structure. One of the first die and the second die has a pad and a cap layer disposed over the pad. The cap layer exposes a portion of a top surface of the pad, and the portion of the top surface of the pad has a probe mark. A bonding metal layer of the hybrid bonding structure penetrates the cap layer to electrically connect to the pad. A method of fabricating the first die or the second die of 3DIC structure is also provided.

A method of fabricating a semiconductor package includes forming a capping pattern on a chip pad of a semiconductor device. The semiconductor device includes a passivation pattern that exposes a portion of the chip pad, and the capping pattern covers the chip pad. The method further includes forming a redistribution layer on the capping pattern. Forming the redistribution layer includes forming a first insulation pattern on the capping pattern and the passivation pattern, forming a first opening in the first insulation pattern by performing exposure and development processes on the first insulation pattern, in which the first opening exposes a portion of the capping pattern, and forming a redistribution pattern in the first opening.

Provided is a semiconductor structure including a substrate, an interconnect structure, a pad, a protective layer, and a bonding structure. The interconnect structure is disposed over the substrate. The pad is disposed over and electrically connected to the interconnect structure. A top surface of the pad has a probe mark and the probe mark has a concave surface. The protective layer conformally covers the top surface of the pad and the probe mark. The bonding structure is disposed over the protective layer. The bonding structure includes a bonding dielectric layer and a first bonding metal layer penetrating the bonding dielectric layer and the protective layer to electrically connect to the pad. A method of manufacturing the semiconductor structure is also provided.

Provided is a semiconductor structure including a substrate, an interconnect structure, a pad, a protective layer, and a bonding structure. The interconnect structure is disposed over the substrate. The pad is disposed over and electrically connected to the interconnect structure. A top surface of the pad has a probe mark and the probe mark has a concave surface. The protective layer conformally covers the top surface of the pad and the probe mark. The bonding structure is disposed over the protective layer. The bonding structure includes a bonding dielectric layer and a first bonding metal layer penetrating the bonding dielectric layer and the protective layer to electrically connect to the pad. A method of manufacturing the semiconductor structure is also provided.

Provided is a three-dimensional integrated circuit (3DIC) structure including a first die and a second die bonded together by a hybrid bonding structure. One of the first die and the second die has a pad and a cap layer disposed over the pad. The cap layer exposes a portion of a top surface of the pad, and the portion of the top surface of the pad has a probe mark. A bonding metal layer of the hybrid bonding structure penetrates the cap layer to electrically connect to the pad. A method of fabricating the first die or the second die of 3DIC structure is also provided.

In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of the first and second pads are exposed, a first surface-metal-layer provided on the part of the first pad and a part of the passivation film, and a second surface-metal-layer provided on the part of the second pad and another part of the passivation film. Respective wires are electrically connected to the first and second surface-metal-layers. The semiconductor chip and the respective wires are then sealed with a resin.

Provided is a die stack structure including a first die and a second die. The first die and the second die are bonded together through a hybrid bonding structure. A bonding insulating layer of the hybrid bonding structure extends to contact with one interconnect structure of the first die or the second die.

A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.