Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

Disclosed herein is a semiconductor device that includes a semiconductor die and a substrate including a first surface and a second surface. The substrate includes a conductive circuit and an insulative material over the conductive circuit. The semiconductor die is attached to the second surface. The semiconductor device further includes a metal barrier layer plated onto a functional copper layer etched to form the conductive circuit. The conductive circuit has a thickness of less than or equal to 3 m. Further disclosed is a method of making a semiconductor device.

A semiconductor package that include first and second semiconductor chips bonded together, wherein the first semiconductor chip includes a first semiconductor substrate, a first semiconductor element layer and a first wiring structure sequentially stacked on a first surface of the first semiconductor substrate, first connecting pads and first test pads on the first wiring structure, and first front-side bonding pads, which are connected to the first connecting pads, wherein the second semiconductor chip includes a second semiconductor substrate, a second semiconductor element layer and a second wiring structure sequentially stacked on a third surface of the second semiconductor substrate, and first back-side bonding pads bonded to the first front-side bonding pads on the fourth surface of the second semiconductor substrate, and wherein the first test pads are not electrically connected to the second semiconductor chip.

A semiconductor device includes a pad group including pads provided on a semiconductor substrate and arranged in a row to form a pad row as a whole. The pad group includes at least one first pad provided with a first via-connection part electrically connected therewith and extending in a first direction perpendicular to a row direction of the pad row, and at least one second pad provided with a second via-connection part electrically connected therewith and extending in a second direction opposite to the first direction. The at least one second pad is formed at a position moved in the first direction from the row direction of the pad row passing through a center of the at least one first pad.

Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

A semiconductor device with an under-bump metallurgy (UBM) over a dielectric is provided. The UBM has a trench configured to be offset from a central point of the UBM. A distance between a center of the trench to an edge of the UBM is larger than a distance between the center of the trench to an opposite edge of the UBM. A probe pin is configured to contact the UBM and collect measurement data.

A memory device includes a memory die bonded to a logic die via a wafer-on-wafer bond. A controller of the memory device that is coupled to the memory die can activate a row of the memory die. Responsive to activating the row, a sense amplifier stripe of the memory die can latch a first plurality of signals. A transceiver can route a second plurality of signals from the sense amplifier stripe to the logic die.

A semiconductor package includes a first semiconductor chip having a first substrate, a first insulating layer on the first substrate, and a plurality of first bonding pads on the first insulating layer, and having a flat upper surface by an upper surface of the first insulating layer and upper surfaces of the plurality of first bonding pads; and a second semiconductor chip on the upper surface of the first semiconductor chip and having a second substrate, a second insulating layer below the second substrate and in contact with the first insulating layer, and a plurality of second bonding pads on the second insulating layer and in contact with the first bonding pads, respectively, wherein the first insulating layer includes an insulating interfacial layer in contact with the second insulating layer, embedded in the first insulating layer, and spaced apart from the plurality of first bonding pads.

A memory tile with a probe pad arrangement and a stacked memory device are provided. The memory tile has a first and a second surfaces; a first probe pad set, having first probe pads and provided on the first surface; a second probe pad set, having second probe pads and provided on the second surface; first conductive connections, each of which is connected to a corresponding first probe pad; second conductive connections, each of which is connected to a corresponding first conductive connection; third conductive connections, each of which is connected to a corresponding second conductive connection; and fourth conductive connections, each of which is connected to a corresponding third conductive connection and to a corresponding second probe pad. The first and the second probe pad sets have the same arrangement pattern, and the same test signal pattern.

Protection from electrostatic discharge (ESD) events is provided by forming leading points of discharge (LPoD) structures on a semiconductor die or on a composite die. The LPoD structures may comprise an upper protrusion portion on an ESD path metal structure, intermediate metallic material portions, solder material portions having a greater height than normal solder material portions that are not provided with ESD protection, or a elongated metal bar structure. The LPoD structures may be used for anisotropic etch process for forming via cavities, bonding processes using solder material portions, bonding processes using metal-to-metal bonding, and/or solder ball attachment processes.