Embodiments disclosed herein include semiconductor devices. In one embodiment, a die comprises a substrate, where the substrate comprises a semiconductor material. In an embodiment, a backend layer is over the substrate, where the backend layer comprises conductive routing. In an embodiment, the die further comprises a protrusion extending out from an edge of the substrate and the backend layer. In an embodiment, a fiducial is on a surface of the protrusion.

A method includes forming a first dielectric layer on a first wafer, and forming a first bond pad penetrating through the first dielectric layer. The first wafer includes a first semiconductor substrate, and the first bond pad is in contact with a first surface of the first semiconductor substrate. The method further includes forming a second dielectric layer on a second wafer and forming a second bond pad extending into the second dielectric layer. The second wafer includes a second semiconductor substrate. The first wafer is sawed into a plurality of dies, with the first bond pad being in a first die in the plurality of dies. The first bond pad is bonded to the second bond pad.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure, a second semiconductor structure, a through semiconductor via, and an insulation layer. The first semiconductor structure includes a first circuit layer and a first main bonding layer in the first circuit layer and substantially coplanar with a front face of the first circuit layer. The second semiconductor structure includes a second circuit layer on the first circuit layer and a second main bonding layer in the second circuit layer, and topologically aligned with and contacted to the first main bonding layer. The through semiconductor via is along the second semiconductor structure and the first and second main bonding layer, and extending to the first circuit layer. The insulation layer is positioned on a sidewall of the through semiconductor via.

A light emitting package is provided, the light emitting package includes a carrier having a main part that has multiple chip bonding regions, and each the chip bonding regions has two neighboring conductive parts. An insulating part is disposed on the main part and portion of the two neighboring conductive parts, and multiple hollow-out structures are formed by the insulating part and corresponded in position to the chip bonding regions. Each of the hollow-out structures has a side wall that surrounds the chip bonding regions, and the portion of the tops of the two neighboring conductive parts are exposed from a bottom portion of the hollow-out structure, and multiple light emitting chips are disposed onto the chip bonding surfaces.

Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) having a first IC structure that includes a first substrate, a first interconnect structure, and a first hybrid bond structure. The second IC structure includes a second substrate and a second hybrid bond structure abutting the first hybrid bond structure at a bond interface. The second substrate includes first and second device regions including first semiconductor devices and second semiconductor devices. The first semiconductor devices being of a first type of IC device and the second semiconductor devices being of a second type of IC device different than the first type of IC device. A bond routing structure couples the first interconnect structure to the first and second semiconductor devices. A lateral routing structure continuously laterally extends from under the first device region to under the second device region.

A bonded assembly of a primary semiconductor die and a complementary semiconductor die includes first pairs of first primary bonding pads and first complementary bonding pads that are larger in area than the first primary bonding pads, and second pairs of second primary bonding pads and second complementary bonding pads that are smaller in area than the second primary bonding pads.

An element and a bonded structure including the element are disclosed. The element can include a non-conductive region having a cavity extending at least partially through a thickness of the non-conductive region from the contact surface, and a contact feature formed in the cavity. The non-conductive region is configured to directly bond to a non-conductive region of a second element. The contact pad of the element is configured to directly bond to a contact pad of the second element. The contact pad can include a first conductive material and a second conductive material. The first conductive material can have a unit cell size greater than a unit cell size of the second conductive material. The first conductive material can be a metal alloying material. The first conductive material can be a metal silicide and the second conductive material can be a metal. A bonded conductive contact can include a conductive material and an alloying element, and an amount of the alloying element can vary through a thickness of the bonded conductive contact.

A bonding method and a bonding structure are provided. A device substrate is provided including a plurality of semiconductor devices, wherein each of the semiconductor devices includes a first bonding layer. A cap substrate is provided including a plurality of cap structures, wherein each of the cap structures includes a second bonding layer, the second bonding layer having a planar surface and a first protrusion protruding from the planar surface. The device substrate is bonded to the cap substrate by engaging the first protrusion of the second bonding layer of each of the cap structures with the corresponding first bonding layer of each of the semiconductor devices in the device substrate.

Layer structures for making direct metal-to-metal bonds at low temperatures and shorter annealing durations in microelectronics are provided. Example bonding interface structures enable direct metal-to-metal bonding of interconnects at low annealing temperatures of 150° C. or below, and at a lower energy budget. The example structures provide a precise metal recess distance for conductive pads and vias being bonded that can be achieved in high volume manufacturing. The example structures provide a vertical stack of conductive layers under the bonding interface, with geometries and thermal expansion features designed to vertically expand the stack at lower temperatures over the precise recess distance to make the direct metal-to-metal bonds. Further enhancements, such as surface nanotexture and copper crystal plane selection, can further actuate the direct metal-to-metal bonding at lowered annealing temperatures and shorter annealing durations.