A memory device includes a memory die bonded to a logic die via a wafer-on-wafer bond. A controller of the memory device that is coupled to the memory die can activate a row of the memory die. Responsive to activating the row, a sense amplifier stripe of the memory die can latch a first plurality of signals. A transceiver can route a second plurality of signals from the sense amplifier stripe to the logic die.

Methods, systems, and devices related to a memory die and a logic die having a wafer-on-wafer bond therebetween. A memory die can include a memory array and a plurality of input/output (IO) lines coupled thereto. A logic die can include to a deep learning accelerator (DLA). The memory die can be coupled to the logic die by a wafer-on-wafer bond. The wafer-on-wafer bond can couple the plurality of IO lines to the DLA.

A wafer-on-wafer bonded memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. A memory device formed on a memory die can include many global input/output lines and many arrays of memory cells. Each array of memory cells can include respective local input/output (LIO) lines coupled to a global input/output line. A logic device can be formed on a logic die. A bond, formed between the memory die and the logic die via a wafer-on-wafer bonding process, can couple the many global input/output lines to the logic device.

A wafer-on-wafer formed memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. The memory die can be formed as one of many memory dies on a first semiconductor wafer. The logic die can be formed as one of many logic dies on a second semiconductor wafer. The first and second wafers can be bonded via a wafer-on-wafer bonding process. The memory and logic device can be singulated from the bonded first and second wafers.

Methods, systems, and devices related to forming a wafer-on-wafer bond between a memory die and a logic die. A plurality of first metal pads can be formed on a first wafer and a plurality of second metal pads can be formed on a second wafer. A subset of the first metal pads can be bonded to a subset of the second metal pads via a wafer-on-wafer bonding process. Each of a plurality of memory devices on the first wafer can be aligned with and coupled to at least a respective one of a plurality of logic devices on the second wafer. The bonded first and second wafers can be singulated into individual wafer-on-wafer bonded memory and logic dies.

A wafer-on-wafer formed memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of a genetic sequence from the memory die and through a wafer-on-wafer bond. The logic die can also perform a genome annotation lotic operation to attach biological information to the genetic sequence. An annotated genetic sequence can be provided as an output.

A wafer-on-wafer bonded memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. Memory devices can be formed on a first wafer. First metal pads can be formed on the first wafer and coupled to the memory devices. The memory devices can be tested via the first metal pads. The first metal pads can be removed from the first wafer. Subsequently, second metal pads on the first wafer can be bonded, via a wafer-on-wafer bonding process, to third metal pads on a second wafer. Each memory device on the first wafer can be aligned with and coupled to a respective logic device on the second wafer.

A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data. The inputs and the outputs to the VV units can be configured based on a mode of the logic die.

An electrical device includes a substrate, an insulating layer supported by the substrate, and an electrically conductive vertical interconnect disposed in a via hole of the insulating layer. The insulating layer may be configured to provide a coefficient of thermal expansion (CTE) that is equal to or greater than a CTE of the vertical interconnect to thereby impart axial compressive forces at opposite ends of the interconnect. The vertical interconnect may be a hybrid interconnect structure including a low CTE conductor post having a pocket that contains a high CTE conductor contact. At low operating temperatures, the high CTE conductor contact is under tension due to the higher CTE, and thus the high CTE conductor contact relieves strain in the device by void expansion and elongation.

A chip package on package structure includes a primary chip stack unit having pins insulated and spaced from each other on a first surface; a first bonding layer disposed on the first surface, where the first bonding layer includes bonding components insulated and spaced from each other, each bonding component includes a bonding part, and any two bonding parts are insulated and have a same cross-sectional area, and the bonding components are separately bonded to the pins; and secondary chip stack units, disposed on a surface of a side that is of the first bonding layer and that is away from the primary chip stack unit, where the secondary chip stack unit has micro bumps insulated and spaced from each other, and each of the micro bumps is bonded to one of the bonding components.