A display apparatus includes a first base substrate defining: an outer edge thereof at which a side surface is exposed, and an upper surface thereof connected to the outer edge; first and second guiding dams on the upper surface and extending from an inside of the first base substrate to the outer edge; a first signal line on the upper surface and extending between the first and second guiding dams from the inside of the first base substrate to the outer edge thereof; and a first side pad connected to the first signal line. The first side pad includes a first horizontal portion on the upper surface and extending between the first and second guiding dams, in a top plan view, and the first horizontal portion extending to define a first vertical portion which is disposed on the side surface.

There is provided a semiconductor device, including a semiconductor substrate, an interlayer insulating layer formed on the semiconductor substrate, a bonding electrode formed on a surface of the interlayer insulating layer, and a metal film which covers an entire surface of a bonding surface including the interlayer insulating layer and the bonding electrode.

There is provided a semiconductor device, including a semiconductor substrate, an interlayer insulating layer formed on the semiconductor substrate, a bonding electrode formed on a surface of the interlayer insulating layer, and a metal film which covers an entire surface of a bonding surface including the interlayer insulating layer and the bonding electrode.

There is provided a semiconductor device, including a semiconductor substrate, an interlayer insulating layer formed on the semiconductor substrate, a bonding electrode formed on a surface of the interlayer insulating layer, and a metal film which covers an entire surface of a bonding surface including the interlayer insulating layer and the bonding electrode.

There is provided a semiconductor device, including a semiconductor substrate, an interlayer insulating layer formed on the semiconductor substrate, a bonding electrode formed on a surface of the interlayer insulating layer, and a metal film which covers an entire surface of a bonding surface including the interlayer insulating layer and the bonding electrode.

A semiconductor package includes: a package substrate including an insulating layer and a plurality of conductive patterns within the insulating layer and respectively including a wiring portion and a via portion; a semiconductor chip on the package substrate and connected to the plurality of conductive patterns; and a molding member that covers the package substrate and the semiconductor chip. The semiconductor chip is closer to a second edge than to an opposite first edge of the package substrate, the plurality of conductive patterns includes a first conductive pattern overlapping a first side surface of the semiconductor chip in a vertical direction and a second conductive pattern overlapping a second side surface of the semiconductor chip in a vertical direction, and a thickness in the vertical direction of a wiring portion of the first conductive pattern is different from a thickness of a wiring portion of the second conductive pattern.