A method includes bonding a tier-1 device die to a carrier, forming a first gap-filling region to encapsulate the tier-1 device die, forming a first redistribution structure over and electrically connected to the tier-1 device die, and bonding a tier-2 device die to the tier-1 device die. The tier-2 device die is over the tier-1 device die, and the tier-2 device die extends laterally beyond a corresponding edge of the tier-1 device die. The method further includes forming a second gap-filling region to encapsulate the tier-2 device die, removing the carrier, and forming a through-dielectric via penetrating through the first gap-filling region. The through-dielectric via is overlapped by, and is electrically connected to, the tier-2 device die. A second redistribution structure is formed, wherein the first redistribution structure and the second redistribution structure are on opposing sides of the tier-1 device die.

A die stack structure including a first die, an encapsulant, a redistribution layer and a second die is provided. The encapsulant laterally encapsulates the first die. The redistribution layer is disposed below the encapsulant, and electrically connected with the first die. The second die is disposed between the redistribution layer and the first die, wherein the first and second dies are electrically connected with each other, the second die comprises a body portion having a first side surface, a second side surface and a curved side surface therebetween, and the curved side surface connects the first side surface and the second side surface.

A semiconductor package includes: a first semiconductor chip including a plurality of front surface pads disposed on a first active surface of a first semiconductor substrate, at least one penetrating electrode penetrating at least a portion of the first semiconductor substrate and connected to the front surface pads, a first rear surface cover layer disposed on a first inactive surface of the first semiconductor substrate, a first rear surface dummy conductive layer penetrating a portion of the first rear surface cover layer; a second semiconductor chip including a second front surface cover layer disposed on a second active surface of a second semiconductor substrate, and a second front surface dummy conductive layer penetrating a portion of the second front surface cover layer; and at least one first bonded pad penetrating the first rear surface cover layer and the second front surface cover layer.

A package device includes a first device die and second device die bonded thereto. When the area of the second device die is less than half the area of the first device die, one or more inactive structures having a semiconductor substrate is also bonded to the first device die so that the combined area of the second device die and the one or more inactive structures is greater than half the area of the first device die.

A semiconductor device includes a first semiconductor die, a second semiconductor die including a side surface bonded to the first semiconductor die, such that the second semiconductor die is perpendicular to the first semiconductor die, and a junction circuit for connecting the first semiconductor die to the second semiconductor die.

A semiconductor device includes a first substrate having a first surface, and a second substrate having a second surface in contact with the first surface. The first substrate includes a first circuit, a first electrode having a first connection end on the first surface, and a first auxiliary electrode having a second connection end on the first surface. The first electrode is connected to the first circuit inside the first substrate, and the first auxiliary electrode is connected to the first electrode. The second substrate includes a second circuit and a second electrode having a third connection end on the second surface. The second electrode is connected to the second circuit. The third connection end is connected directly with the first connection end and the second connection end. The second electrode is connected directly with the first electrode and through the first auxiliary electrode to the first electrode.

In one embodiment, a semiconductor device includes a lower interconnect layer including a plurality of lower interconnects, and a plurality of lower pads provided on the lower interconnects. The device further includes a plurality of upper pads provided on the lower pads and being in contact with the lower pads, and an upper interconnect layer including a plurality of upper interconnects provided on the upper pads. The lower pads include a plurality of first pads and a plurality of second pads. The upper pads include a plurality of third pads provided on the second pads and a plurality of fourth pads provided on the first pads, a lower face of each third pad is larger in area than a upper face of each second pad, and a lower face of each fourth pad is smaller in area than a upper face of each first pad.

A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.

A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.

Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.