A reinforcing resin composition includes: an epoxy compound (A); and an amine compound (B) including at least one selected from the group consisting of a compound (B1) represented by a formula (1), a compound (B2) represented by a formula (2), a compound (B3) represented by a formula (3), a compound (B4) represented by a formula (4), and a compound (B5) represented by a formula (5).

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Disclosed is a package structure, including a first substrate, a second substrate, a bonding pad, a protective layer, and an air gap. The first substrate has a first surface and a second surface opposite to each other, and includes a first via extending from the first surface to the second surface. The second substrate is disposed on the first surface of the first substrate, has a third surface facing the first surface and a fourth surface opposite to the third surface, and includes a second via extending from the third surface to the fourth surface. The bonding pad is disposed between the first and second substrates and connected to the first and second vias. The protective layer is disposed between the first and second substrates, and surrounds the bonding pad. The air gap is disposed between the first and second substrates.

A test method and system of testing a semiconductor device is provided. The method includes placing a packaged semiconductor device on a tester and engaging a thermal management component with an upper surface of the packaged semiconductor device. The packaged semiconductor device is tested using the tester, and during the testing a first thermal condition is delivered to a first region of the thermal management component while delivering a second thermal condition is delivered to a second region of the thermal management component. The first thermal condition is different than the second thermal condition.

A method of manufacturing a silicon photonics chip may comprise: forming a terrace structure on one surface of a substrate, wherein the terrace structure has a bottom surface of a trench structure formed on the one surface and a plurality of vertical stoppers in a form of a pedestal that protrude integrally with the substrate from the bottom surface, and each of the plurality of vertical stoppers includes a body, an oxide layer formed on an upper surface of the body, and a waveguide layer formed on the oxide layer; forming an under bump metallization (UBM) layer on the bottom surface; forming solder bumps on a light source element; and performing flip-chip bonding of the light source element on which the solder bumps are formed onto the terrace structure so that the solder bumps comes into contact with the UBM layer.

Semiconductor device (50) includes: semiconductor element (1) having a plurality of electrode terminals (2); bump (8) formed on each of the plurality of electrode terminals (2) and having tapering part (8a) that narrows with distance from a side close to corresponding one of electrode terminals (2); and buffer part (3c) covered with bump (8).

A method includes forming a conductive pillar over and connecting to a conductive pad, dispensing a first polymer layer, wherein the first polymer layer contacts a lower portion of a sidewall of the conductive pillar, curing the first polymer layer, and dispensing a second polymer layer on the first polymer layer. The second polymer layer contacts an upper portion of the sidewall of the conductive pillar. The second polymer layer is then cured.

In an electronic module, electrode pads of a first circuit component and electrode pads of a second circuit component are arranged such that conductive bonding members disposed between the electrode pads of the first circuit component and the electrode pads of the second circuit component form bonding member groups, each of which includes two or more conductive bonding members arranged along one direction in a plane direction of the first circuit component, with the one direction being defined as an extension direction of each of the bonding member groups. Each of reinforcing members is disposed apart from an adjacent bonding member group among the bonding member groups, and each of the reinforcing members has a first portion that extends along a direction intersecting with the extension direction of the adjacent bonding member group, and a second portion that extends along the extension direction of the adjacent bonding member group.

A test method and system of testing a semiconductor device is provided. The method includes placing a packaged semiconductor device on a tester and engaging a thermal management component with an upper surface of the packaged semiconductor device. The packaged semiconductor device is tested using the tester, and during the testing a first thermal condition is delivered to a first region of the thermal management component while delivering a second thermal condition is delivered to a second region of the thermal management component. The first thermal condition is different than the second thermal condition.

Provided is a semiconductor package with improved reliability. The semiconductor package includes: a plurality of connection terminals on a first surface of the semiconductor device; a protection member on the first surface of the semiconductor device and partially covers side surfaces of the plurality of connection terminals such that the protective member exposes lower surfaces of the plurality of connection terminals; and a mold member that covers a side surface of the semiconductor device and a portion of the protection member such that the mold member does not cover the lower surfaces of the plurality of connection terminals.

In examples, a semiconductor package comprises a substrate having multiple conductive layers coupled to bond pads at a surface of the substrate. The package includes a semiconductor die including a device side facing the substrate, the device side having first and second circuitry regions, the first circuitry region having greater sensitivity to at least one of mechanical or thermal stress than the second circuitry region. The package also includes conductive members coupled to the bond pads of the substrate, in direct physical contact with the second circuitry region, and not in direct physical contact with the first circuitry region. The package further comprises a first support member coupled to the device side of the semiconductor die and extending toward the substrate and not touching the substrate or a second support member coupled to the substrate. The package also includes a ring on the substrate and encircling the bond pads and a glob top member covering the semiconductor die and a portion of the substrate circumscribed by the ring. The package also includes a mold compound covering the glob top member and the substrate.