The present disclosure relates to a semiconductor structure. The semiconductor structure includes a semiconductor unit, one or more bonding structures, and at least one supporter. The semiconductor unit includes at least one via. The one or more bonding structures are disposed over the semiconductor unit and electrically connected to the at least one via. The at least one supporter is disposed over the semiconductor unit. The at least one supporter is a metal block or a polymer block spaced apart from the one or more bonding structures.

A method for forming a semiconductor structure includes: providing a semiconductor substrate having a first pad and a second pad on a top surface of the semiconductor substrate; providing a circuit board having an active pad and a non-metallic surface; providing a first solder ball and a second solder ball on the active pad and the non-metallic surface respectively; attaching the first pad and the second pad on the first solder ball and the second solder ball respectively; and reflowing the first solder ball and the second solder ball to form a first bump wetted on the active pad and a second bump not wetted on the non-metallic surface.

An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material.

A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.

In a described example, an apparatus includes a semiconductor substrate and at least two pillar bumps formed on an active surface of the semiconductor substrate, the at least two pillar bumps extending away from the active surface and having ends spaced from the semiconductor substrate with solder material at the ends of the at least two pillar bumps. At least one spacer is formed on the active surface of the semiconductor substrate, the at least one spacer extending a predetermined distance from the active surface of the semiconductor substrate. A package substrate has a die mount area on a first surface including portions receiving the ends of the at least two pillar bumps and receiving an end of the at least one spacer. Mold compound covers the semiconductor substrate, the at least two pillars, the at least one spacer, and at least a portion of the semiconductor substrate.

The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure has a first conductive layer on a first substrate and a second conductive layer on a second substrate. A bonding structure is disposed between the first conductive layer and the second conductive layer. A support structure is disposed between the first substrate and the second substrate. A passivation layer covers a bottom surface of the first conductive layer and has a lower surface facing an uppermost surface of the support structure.

A semiconductor package structure includes a first package, a second package over the first package, a plurality of connectors between the first package and the second package and a plurality of baffle structures between the first package and the second package. The second package includes a bonding region and a periphery region surrounding the bonding region. The connectors are disposed in the bonding region to provide electrical connections between the first package and the second package. The baffle structures are disposed in the periphery region and are separated from each other.

Some embodiments of the present disclosure relate to an integrated circuit. The integrated circuit has a first semiconductor die and a second semiconductor die. The first semiconductor die is bonded to the second semiconductor die by one or more bonding structures. A first plurality of support structures are disposed between the first semiconductor die and the second semiconductor die. The first plurality of support structures are spaced apart from the one or more bonding structures. The first plurality of support structures are configured to hold together the first semiconductor die and the second semiconductor die.

An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material.

An electronic assembly and methods of making the assembly are disclosed. The electronic assembly includes a substrate with an elastic member having an intrinsic stress profile. The elastic member has an anchor portion on the surface of the substrate; and a free end biased away from the substrate via the intrinsic stress profile to form an out of plane structure. The substrate includes one or more spacers on the substrate. The electronic assembly includes a chip comprising contact pads. The out of plane structure on the substrate touches corresponding contact pads on the chip, and the spacers on the substrate touch the chip forming a gap between the substrate and the chip.