Patent classifications
H01L2224/10155
Substrate, electronic substrate, and method for producing electronic substrate
A substrate is capable of effectively reinforcing a connecting portion between an electronic component and the substrate. The substrate is a substrate on which a first electronic component having a plurality of bumps is to be mounted, and includes a base portion including an insulator and having, on the upper face thereof, at least one groove portion configured to store a tip portion of at least one of the bumps, and includes an electrode formed on at least the bottom face of the groove portion.
INTERPOSER, ELECTRONIC SUBSTRATE, AND METHOD FOR PRODUCING ELECTRONIC SUBSTRATE
An interposer is capable of efficiently reinforcing the connecting portion between an electronic component and a substrate. The interposer is used for mounting a first electronic component on a substrate and includes a sheet-shaped spacer having at least one through-hole and including a material that does not flow during reflow soldering and a resin portion that covers at least a part of the spacer and is flowable during reflow soldering, and the through-hole is configured to store a bump of the first electronic component.
SUBSTRATE, ELECTRONIC SUBSTRATE, AND METHOD FOR PRODUCING ELECTRONIC SUBSTRATE
A substrate is capable of effectively reinforcing a connecting portion between an electronic component and the substrate. The substrate is a substrate on which a first electronic component having a plurality of bumps is to be mounted, and includes a base portion including an insulator and having, on the upper face thereof, at least one groove portion configured to store a tip portion of at least one of the bumps, and includes an electrode formed on at least the bottom face of the groove portion.
Interposer, electronic substrate, and method for producing electronic substrate
An interposer is capable of efficiently reinforcing the connecting portion between an electronic component and a substrate. The interposer is used for mounting a first electronic component on a substrate and includes a sheet-shaped spacer having at least one through-hole and including a material that does not flow during reflow soldering and a resin portion that covers at least a part of the spacer and is flowable during reflow soldering, and the through-hole is configured to store a bump of the first electronic component.
Tall and fine pitch interconnects
Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.
SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor package structure includes a first package, a second package over the first package, a plurality of connectors between the first package and the second package and a plurality of baffle structures between the first package and the second package. The second package includes a bonding region and a periphery region surrounding the bonding region. The connectors are disposed in the bonding region to provide electrical connections between the first package and the second package. The baffle structures are disposed in the periphery region and are separated from each other.
Method for underfilling using spacers
A method for underfilling an electronic circuit assembly may include mounting one or more structures to a substrate, mounting one or more spacers to the substrate at one or more positions, respectively, to form one or more passages between the one or more spacers and the one or more structures, dispensing underfill to the one or more passages, and curing the underfill to secure the one or more structures to the substrate. The one or more structures may include one or more dies.
Interconnect Crack Arrestor Structure and Methods
A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers.
Interconnect Crack Arrestor Structure and Methods
A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers.
Semiconductor die package and method of manufacture
In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.