A semiconductor light emitting apparatus includes a semiconductor light emitting element having a first electrode and a second electrode; a substrate having first and second wiring pattern layers electrically-connected to the first and second electrodes, respectively, and multiple conductive bonding layer elements provided between the first electrode and the first wiring pattern layer and/or between the second electrode and the second wiring pattern layer.

A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame. A packaged semiconductor device with a reflow wall that surrounds a portion of a solder joint that couples a semiconductor device to a lead frame.

Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.

A semiconductor substrate includes a first dielectric layer, a first patterned conductive layer disposed in the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, and a first bump pad disposed in the second dielectric layer. The first bump pad is electrically connected to the first patterned conductive layer, and the first bump pad has a curved surface surrounded by the second dielectric layer.

A flexible multilayer construction (100) for mounting a light emitting semiconductor device (200) (LESD), includes a flexible dielectric substrate (110) having an LESD mounting region (120), first and second electrically conductive pads (130, 140) disposed in the LESD mounting region for electrically connecting to corresponding first and second electrically conductive terminals of an LESD (200) received in the LESD mounting region, and a first fiducial alignment mark (150) for an accurate placement of an LESD in the LESD mounting region. The first fiducial alignment mark is disposed within the LESD mounting region.

A semiconductor package and a method of fabricating the same. The semiconductor package includes a lower structure including a first lower conductive pad disposed on an upper surface thereof, a first semiconductor chip disposed on the lower structure, the first semiconductor chip including a first chip conductive pad disposed on a lower surface thereof, a solder ball connecting the first lower conductive pad and the first chip conductive pad, a photosensitive insulating layer filling a space between the lower structure and the first semiconductor chip, and a first organic insulating layer covering a side surface of the first chip conductive pad.

A semiconductor device includes a semiconductor element, an internal electrode connected to the semiconductor element, a sealing resin covering the semiconductor element and a portion of the internal electrode, and an external electrode exposed from the sealing resin and connected to the internal electrode. The internal electrode includes a wiring layer and a columnar portion, where the wiring layer has a wiring layer front surface facing the back surface of the semiconductor element and a wiring layer back surface facing opposite from the wiring layer front surface in the thickness direction. The columnar portion protrudes in the thickness direction from the wiring layer front surface. The columnar portion has an exposed side surface facing in a direction perpendicular to the thickness direction. The external electrode includes a first cover portion covering the exposed side surface.

An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a first substrate containing first circuitry, a first contact pad, a first pillar, a first pillar protection layer, a second substrate containing second circuitry, and a solder ball disposed on the first pillar and electrically and mechanically coupling the first substrate to the second substrate. The first contact pad is disposed on the first substrate and coupled to the first circuitry. The first pillar electrically disposed over the first contact pad. The first pillar protection layer is hydrophobic to solder and is disposed on a side surface of the first pillar.

A semiconductor device includes: a substrate with an obverse surface facing in a thickness direction; first and second wirings on the obverse surface; and a semiconductor element with a first electrode facing the obverse surface and an adjacent second electrode facing the obverse surface. The first electrode is electrically bonded to the first wiring, and the second electrode bonded to the second wiring. The substrate includes first, second and third sections, with the first section including a portion of the obverse surface and overlapping with the first wiring and first electrode as viewed in the thickness direction. The second section includes a portion of the obverse surface, overlapping with the second wiring and second electrode as viewed in the thickness direction. The third section, located between the first and the second sections as viewed in the thickness direction, includes a first surface with its normal direction intersecting the thickness direction.

A bump-on-trace (BOT) interconnection in a package and methods of making the BOT interconnection are provided. An embodiment BOT interconnection comprises a landing trace including a distal end, a conductive pillar extending at least to the distal end of the landing trace; and a solder feature electrically coupling the landing trace and the conductive pillar. In an embodiment, the conductive pillar overhangs the end surface of the landing trace. In another embodiment, the landing trace includes one or more recesses for trapping the solder feature after reflow. Therefore, a wetting area available to the solder feature is increased while permitting the bump pitch of the package to remain small.