A solution relating to electronic devices of flip-chip type is provided, which includes at least one chip carrier having a carrier surface, the carrier(s) including one or more contact elements of electrically conductive material on the carrier surface, at least one integrated circuit chip having a chip surface, the chip(s) including one or more terminals of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material soldering each terminal to the corresponding contact element, and a restrain structure around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements. The carrier includes one or more heat dissipation elements of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask.

A device comprises a first package component, and a first metal trace and a second metal trace on a top surface of the first package component. The device further includes a dielectric mask layer covering the top surface of the first package component, the first metal trace and the second metal trace, wherein the dielectric mask layer has an opening therein exposing the first metal trace. The device also includes a second package component and an interconnect formed on the second package component, the interconnect having a metal bump and a solder bump formed on the metal bump, wherein the solder bump contacts the first metal trace in the opening of the dielectric mask layer.

A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame. A packaged semiconductor device with a reflow wall that surrounds a portion of a solder joint that couples a semiconductor device to a lead frame.

A packaged light emitting device can include a mounting substrate including first and second electrode portions that are separated by a recess defined by a first side surface of the first electrode portion and a second side surface of the second electrode portion that is opposite the first side surface. An insulation support member can partially fill a lower portion of the recess to partially cover the first side surface and partially cover the second side surface. A light emitting device can be coupled to the first and second electrode portions of the mounting substrate and a sealing member can be on the mounting substrate covering the light emitting device.

An electronic package, a packaging substrate and a fabricating method are provided, in which a conductive bump pad is formed on an electrical contact pad of the packaging substrate, so that when an electronic element is bonded to the packaging substrate via a solder material in a flip-chip process, the conductive bump pad can guide the flow of the solder material. Therefore, the problem of empty soldering caused by the solder material not effectively contacting with the electrical contact pad can be avoided.

A solution relating to electronic devices of flip-chip type is provided, which includes at least one chip carrier having a carrier surface, the carrier(s) including one or more contact elements of electrically conductive material on the carrier surface, at least one integrated circuit chip having a chip surface, the chip(s) including one or more terminals of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material soldering each terminal to the corresponding contact element, and a restrain structure around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements. The carrier includes one or more heat dissipation elements of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask.

A device comprises a first package component, and a first metal trace and a second metal trace on a top surface of the first package component. The device further includes a dielectric mask layer covering the top surface of the first package component, the first metal trace and the second metal trace, wherein the dielectric mask layer has an opening therein exposing the first metal trace. The device also includes a second package component and an interconnect formed on the second package component, the interconnect having a metal bump and a solder bump formed on the metal bump, wherein the solder bump contacts the first metal trace in the opening of the dielectric mask layer.

An electrical device and a method for the manufacture of an electrical device are specified. The device has a carrier with an upper side and a metallized contact surface arranged on it as well as a solder mask layer which covers a part of the upper side but not the contact surface. The solder mask layer has a thickness of 200 nm or less, thereby facilitating subsequent process steps for encapsulating the device.

A wiring board includes a single-layer insulating layer, and a single-layer interconnect layer embedded in the insulating layer, wherein an entirety of a first surface of the interconnect layer is exposed in a recessed position relative to a first surface of the insulating layer, and a second surface of the interconnect layer is partially exposed in a recessed position relative to a second surface of the insulating layer.

An electronic package and method of manufacture are provided. The method includes providing an electronic module. The electronic module has a group of electrically conductive nodes. The method includes providing a substrate panel, in which a plurality of electrically conductive contact pads are arranged on a surface of the substrate panel, a predetermined one of the plurality of electrically conductive contact pads associated with the group of the electrically conductive nodes. The method includes defining a solder masking arrangement extending over a part of the surface of the substrate panel to overlie the predetermined electrically conductive contact pad such that the masking arrangement at least partially defines a group of spatially distinct fusion areas each associated with a corresponding one of the group of the electrically conductive nodes. The method includes coupling the group of electrically conductive nodes to the group of spatially distinct fusion areas by use of corresponding intermediate solder portions.