An electronic package and method of manufacture are provided. The electronic package has a substrate panel, an electronic module mounted to a surface of the substrate panel, and a plurality of electrically conductive contact pads arranged on the surface of the substrate panel. The electronic module includes a group of electrically conductive nodes. A predetermined one of the plurality of electrically conductive contact pads is associated with the group of electrically conductive nodes. The group of electrically conductive nodes is coupled to a corresponding group of spatially distinct fusion areas of the predetermined electrically conductive contact pad by corresponding intermediate solder portions. A solder masking arrangement extends over a part of the surface of the substrate panel. The masking arrangement is arranged over the predetermined electrically conductive contact pad and configured to at least partially define the group of spatially distinct fusion areas.

A semiconductor chip package assembly includes a package substrate having a chip mounting surface; a plurality of solder pads disposed on the chip mounting surface; a first dummy pad and a second dummy pad spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a chip package mounted on the chip mounting surface and electrically connected to the package substrate through a plurality of solder balls on respective said solder pads; a discrete device having a first terminal and a second terminal disposed between the chip package and the package substrate; a first solder connecting the first terminal with the first dummy pad and the chip package; and a second solder connecting the second terminal with the second dummy pad and the chip package.

A semiconductor substrate includes a first dielectric layer, a first patterned conductive layer disposed in the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, and a first bump pad disposed in the second dielectric layer. The first bump pad is electrically connected to the first patterned conductive layer, and the first bump pad has a curved surface surrounded by the second dielectric layer.

A surface-mount component (10A) having a pair of connection terminals (12a, 12b) with an inter-terminal pitch L2 therebetween is mounted on a circuit substrate (20A) having a pair of electrode pads (22a, 22b) with an inter-electrode pitch L1 therebetween (L2>L1). Standard position indication marks (23) are formed on the circuit substrate (20A). When heating is performed under a state in which solder non-wetting of the left electrode pad (22a) occurs, the solder applied to the right electrode pad (22b) solder connects the right electrode pad (22b) and the connection terminal (12b), and the surface-mount component (10A) is attracted to the left and is offset or displaced from the standard position indication marks (23) by an offset dimension 7. If the solder is applied to the left and right electrode pads (22a, 22b), there is no offset dimension.

A flexible multilayer construction (100) for mounting a light emitting semiconductor device (200) (LESD), includes a flexible dielectric substrate (110) having an LESD mounting region (120), first and second electrically conductive pads (130, 140) disposed in the LESD mounting region for electrically connecting to corresponding first and second electrically conductive terminals of an LESD (200) received in the LESD mounting region, and a first fiducial alignment mark (150) for an accurate placement of an LESD in the LESD mounting region. The first fiducial alignment mark is disposed within the LESD mounting region.

A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame. A packaged semiconductor device with a reflow wall that surrounds a portion of a solder joint that couples a semiconductor device to a lead frame.

A packaged semiconductor device includes a lead frame and a semiconductor device. A solder joint is coupled between the lead frame and a terminal on the semiconductor device. A reflow wall is on a portion of the lead frame and is in contact with the solder joint. A molding compound covers portions of the semiconductor device, the lead frame, the solder joint, and the reflow wall.

A semiconductor package structure includes a substrate, a semiconductor chip, and a solder material. The substrate includes an insulating layer, a conductive circuit layer, and a conductive bump. The conductive circuit layer is recessed from a top surface of the insulating layer. The conductive circuit layer includes a pad, and a side surface of the pad extends along a side surface of the insulating layer. The conductive bump is disposed on the pad. A side surface of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space. A solder material electrically connects the conductive bump and the semiconductor chip. A portion of the solder material is disposed in the accommodating space.

A package substrate includes: an insulating substrate, a first and a second soldering pads spacedly disposed on a first surface of the insulating substrate, a first and a second electrodes spacedly disposed on an opposite second surface of the insulting substrate. The first and the second soldering pads are electrically connected to the first and the second electrodes respectively. Moreover, a first and a second grooves are defined on the first surface of the insulating substrate, the first and the second grooves are spaced from each other and disposed between the first and the second soldering pads. The invention further provides a LED flip chip package structure including the package substrate, a LED flip chip and fluorescent glue. The invention adds the grooves in the spacing between the soldering pads as a buffer space for melted solder flowing during reflow soldering process and therefore can relieve short-circuit phenomenon.

The present disclosure provides a semiconductor package that prevents a bump bridge from being formed between adjacent conductive bumps to realize a fine bump pitch when each unit circuit part is directly stacked without using a printed circuit board and a method for manufacturing the same. The semiconductor package includes a first semiconductor chip structure including a first unit circuit part, a first passivation layer disposed on the first unit circuit part, and a conductive bump electrically connected to the first unit circuit part, and a second semiconductor chip structure including a second unit circuit part, a second passivation layer having a stepped portion that is recessed inward and disposed on the second unit circuit part, and a bump pad provided in the stepped portion. The first semiconductor chip structure and the second semiconductor chip structure are stacked to allow the conductive bump to be bonded to the bump pad within the stepped portion.