An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.

A package carrier includes a carrier and a light absorption layer. The light absorption layer is disposed on the carrier. The light absorption layer includes a notch at the periphery of the carrier, and the notch is light transmissive so as to expose the carrier to light in a normal direction of the carrier. A semiconductor manufacturing process is also provided.

An embodiment includes a first package component including a first integrated circuit die and a first encapsulant at least partially surrounding the first integrated circuit die. The device also includes a redistribution structure on the first encapsulant and coupled to the first integrated circuit die. The device also includes a first thermal module coupled to the first integrated circuit die. The device also includes a second package component bonded to the first package component, the second package component including a power module attached to the first package component, the power module including active devices. The device also includes a second thermal module coupled to the power module. The device also includes a mechanical brace extending from a top surface of the second thermal module to a bottom surface of the first thermal module, the mechanical brace physically contacting the first thermal module and the second thermal module.

A technical object of the present invention is to devise a glass sheet that is suitable for supporting a substrate to be processed to be subjected to high-density wiring and has high end surface strength, and a method of manufacturing the glass sheet, to thereby contribute to an increase in density of a semiconductor package. The glass sheet of the present invention has a total thickness variation of less than 2.0 μm, all or part of an end surface of the glass sheet including a melt-solidified surface.

Apparatuses and methods using a silicon on insulator (SOI) substrate are described. An example apparatus includes: a substrate including a first surface and a second surface opposite to the first surface; a circuit formed in the first surface; a first electrode through the substrate from the first surface to the second surface; and a first insulative film around the first electrode. The first electrode includes: a first portion formed in the substrate; and a second portion continuous to the first portion and protruding from the second surface. The first insulative film is formed between the first portion of the first electrode in the substrate and extending to a side surface of the second portion of the first electrode.

A method of manufacturing a mounting substrate according to an embodiment of the present technology includes the following three steps:

(1) a step of forming a plurality of electrodes on a semiconductor layer, and thereafter forming one of solder bumps at a position facing each of the electrodes;

(2) a step of covering the solder bumps with a coating layer, and thereafter selectively etching the semiconductor layer with use of the coating layer as a mask to separate the semiconductor layer into a plurality of elements; and

(3) a step of removing the coating layer, and thereafter mounting the elements on a wiring substrate to direct the solder bumps toward the wiring substrate, thereby forming the mounting substrate.

A method of manufacturing a semiconductor device includes forming a first via having a first diameter in a first main surface of a semiconductor substrate having a first thickness, after forming a first insulating film on a bottom surface and a side surface of the first via, forming a first through electrode inside the first via a first barrier metal film, after forming the first through electrode, processing the semiconductor substrate from a second main surface on an opposite side of the first main surface to reduce the first thickness of the semiconductor substrate to a second thickness thinner than the first thickness, after processing the semiconductor substrate, forming a third insulating film on the second main surface of the semiconductor substrate, and after forming the third insulating film, sequentially processing the third insulating film and the semiconductor substrate.

Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects.

An integrated radio frequency (RF) circuit structure may include an active device on a first surface of an isolation layer. The integrated RF circuit structure may also include backside metallization on a second surface opposite the first surface of the isolation layer. A body of the active device is biased by the backside metallization. The integrated RF circuit structure may further include front-side metallization coupled to the backside metallization with a via. The front-side metallization is arranged distal from the backside metallization. The front-side metallization, the via, and the backside metallization may at least partially enclose the active device.

A method for manufacturing a semiconductor apparatus, including preparing a first substrate provided with a pad optionally having a plug and a second substrate or device provided with a plug, forming a solder ball on at least one of the pad or plug of first substrate and the plug of second substrate or device, covering at least one of a pad-forming surface of first substrate and a plug-forming surface of second substrate or device with a photosensitive insulating layer, forming an opening on the pad or plug of the substrate or device that has been covered with photosensitive insulating layer by lithography, pressure-bonding the second substrate or device's plug to the pad or plug of first substrate with the solder ball through the opening, electrically connecting pad or plug of first substrate to second substrate or device's plug by baking, and curing photosensitive insulating layer by baking.